Abstract: In AM radio receivers it is desirable to operate the automatic gain control so that strong signals are actually heard louder than weaker signals. This means that when AM stereo is incorporated into the radio, using a limiter and phase demodulator to recover the L-R stereo information, some means must be provided to cope with the variable L+R signal level. Typically this is done by using a gain control characteristic that eliminates the desired variable sound level. In the invention an absolute value detector is employed as an AM demodulator, the d-c output of which is related to the L+R signal content. A multiplier is coupled between the phase demodulator L-R output and the matrix in which the L+R and L-R signals are combined to produce the separate L and R signals. The multiplier is biased by the d-c component at the AM detector. Thus, as the L+R level varies, the L-R out of multiplier is varied to match.
Abstract: In an FM receiver a multiplier is driven from the IF limiter. The limiter also drives a single tuned circuit which produces a quadrature signal that drives a second port in the multiplier. When the quadrature signal is multiplied by the IF signal an FM detector results. The center frequency is determined by the frequency of the quadrature relationship and the extent of the resultant output curve is determined by the Q of the tuned circuit. The output response is linearized by varying the current in the multiplier as a function of the IF signal deviation.
Abstract: A composite transistor suitable for use in monolithic integrated circuits is characterized as having extremely high current gain, stable operation and low leakage current. Two vertical NPN transistors are coupled into a circuit configuration, along with two lateral PNP transistors, that has three terminals. These terminals behave as a single NPN transistor having characteristics that are superior to those of a conventional NPN transistor.
Abstract: An Electrically Erasable Programmable Read-Only Memory (EEPROM) requires only a single voltage applied to a single control gate for both erasing and writing operations. Writing is accomplished by hot channel electron injection to charge the floating gate of a selected device with electrons. Nonselected devices are kept from charging by either floating their sources or grounding their gates. Devices are erased by grounding the source and drain regions and causing the electrons stored in the floating gates to tunnel to the control gate. Preferred ratioing of the intra-device capacitances prevents erasure of nonselected devices during writing.
Abstract: An automatic self-adjusting processing apparatus for plating an object is described. The apparatus has a plating head, an apparatus coupled to the plating head which is responsive to the presence of the object for indicating the relative position of the plating head and the object, and an apparatus coupled to the indicating apparatus for automatically adjusting, if necessary, the relative position of the plating head and the object to a predetermined relative position.
Abstract: A decoder for obtaining the L-R information in an AM stereo radio receiver. The decoder is basically a four-quadrant multiplier that has one pair of inputs driven from a limiter that operates from the receiver intermediate frequency amplifier. The limiter also drives a tuned circuit which in turn drives the other two multiplier inputs in phase quadrature with the first input pair. The multiplier output is frequency modulation responsive which, when integrated, produces a phase modulation response. The integration is produced by a capacitor connected across the multiplier output terminals. The decoder also includes a large parallel connected inductor that resonates the integrating capacitor at a frequency at the low end of the audio range. This inductor acts as a d-c short at the decoder output and sets the decoder response to the setaudible stereo pilot signal. The inductor is simulated with integrated circuit components.
Abstract: In the fabrication of semiconductor devices it has been found useful to employ plasma etching to create contact holes in the insulating layers that cover the wafers being processed. In particular, when wafers are being fabricated that employ small diameter contacts, it is difficult to ensure that all contact holes are created simultaneously. If etching is continued sufficiently to make sure that all of the contact holes over the wafer are fully etched, it is found that a certain proportion are overetched. If the silicon semiconductor is converted to a metal silicide in the region where contact is to be made subsequently, its plasma etch rate can be reduced sufficiently to avoid overetching.
Abstract: A current comparator is supplied with differential currents based upon an amplitude modulated radio frequency carrier. The comparator outputs are summed in a combining stage the output of which will contain a direct current proportional to the average carrier level and a current variation which represents the carrier modulation. The circuit provides very efficient detection of the modulated carrier.
Abstract: A tape assembly process attaches semiconductor chips to a tape via thermocompression gang bonding and the tape is wound onto a reel. The tape is fabricated during its manufacture to have a plurality of spaced finger array patterns. The inner finger ends are located so as to mate with the bonding pads of a semiconductor device and are bonded thereto. A ring-shaped strip is included in each finger pattern that joins all of the fingers in each pattern into a unitary structure in which the fingers are accurately spaced. Where the ring joins onto the fingers, weakened regions are introduced and the side of the tape that contains the semiconductor device includes a recess that is in registry with the ring. A ceramic substrate that will ultimately mount the semiconductor device is provided with an array of conductor patterns that match the tape finger patterns. A layer of sealing glass is screened over the ceramic, so as to align with the ring.
Abstract: A floating gate memory cell has its control gate self-aligned to the floating gate in the source to drain direction and its floating gate self-aligned to the channel region in that direction and the direction transverse thereto without overlaying the field oxide.
Abstract: A mechanical shock and impact resistant ceramic semiconductor package is formed by applying a resilient, non-conductive, non-absorbent, heat-resistant material onto the surfaces of said package. In a dual in-line ceramic package a silicone polymer is discretely applied onto at least one end of the longitudinally opposite end edge surfaces. This renders the package mechanical shock and impact resistant.
August 18, 1980
Date of Patent:
October 26, 1982
National Semiconductor Corporation
Sally K. Hinds, Peter M. Weiler, Robert R. Hewitt
Abstract: A unity gain amplifier circuit has a control characteristic which permits a variation of the high frequency roll off as a function of a control voltage. Means are provided to prevent a change of output voltage resulting from the control voltage variation.
Abstract: A protection circuit for bulk-silicon CMOS circuits detects the latch-up of parasitic SCR devices, current starves the CMOS circuit in response to detecting a SCR latch-up condition and reenables normal circuit operation once the latch-up condition has been terminated.
Abstract: A pair of differentially related currents are caused to flow in a pair of current modes. A symmetrical current mirror is coupled to the nodes and level shifting means coupled from each node to the current mirror common terminal. A pair of output transistors have their bases directly coupled to the nodes and their emitters cross coupled to the same nodes so that when the nodes are driven to a one V.sub.BE differential, output collector current will flow. The output transistors have their collectors commonly coupled to the circuit output. Deadband control means are connected to the current mirror common terminal so that no output current will flow until the deadband differential is exceeded.
Abstract: A method of fabricating a high-frequency bipolar transistor structure wherein the emitter, higher impurity concentration base, and lower impurity concentration base regions are defined in a single masking operation. Permeation etching is used to etch regions of an oxide layer under a layer of resist which defines regions of the higher impurity concentration thereby simultaneously defining the emitter and lower impurity concentration base regions. The higher impurity concentration base regions are formed by ion implantation of impurities through the unetched oxide regions. The resist is then removed and the lower impurity concentration base and emitters are formed through the resulting opening in the oxide. This results in the self-aligning of the emitter regions with respect to the base regions.
June 18, 1980
Date of Patent:
September 7, 1982
National Semiconductor Corporation
Bert L. Allen, Robert L. Wourms, Daniel C. Hu
Abstract: A bubble memory chip includes a plurality of data loops, some of which may be defective, for storing magnetic bubbles representative of data therein. A serial-parallel input propagation path and a parallel-serial output propagation path are provided for propagating bubbles to and from the data loops. A plurality of spaced apart permalloy disk elements are provided, each adapted for having a single bubble circulated thereabout in the presence of an in-plane rotating magnetic drive field. A stream of bubbles representative of an error map indicating which of the data loops are defective is loaded onto and read from the disk elements to initialize the memory. A plurality of gates permit the bubbles of the error map to be transferred between an error map propagation path and the disk elements in parallel fashion upon pulsing of an adjacent control conductor. The potential for data scrambling in the error map is eliminated.
Abstract: A differential oscillator is supplied with a constant total current. A signal-controlled single-ended shunt circuit bypasses current around the oscillator thus varying the tail current oppositely. This in turn varies the signal delay in the oscillator transistors and hence oscillator frequency.
Abstract: In an amplifier circuit the output devices are thermally coupled to a shutdown circuit. A first latch is designed to operate at a first high temperature excursion. The first latch operation acts to shut the output devices off and to invoke a second latch. The second latch operates between a low temperature and a second high temperature that is below the first high temperature. Thus, after the first latch operates, the second latch will operate to cycle between a low temperature whereupon it energizes the output devices and a high temperature at which it deenergizes the output devices. By this action, the circuit will permit only one high temperature peak after which it will cycle between a lower high temperature peak and a low temperature. This avoids repeated cycling to a high temperature that could be deleterious to the circuit devices or the package in which they are housed.
Abstract: An integrated circuit is employed to provide a high gain signal amplifier having an automatic gain control function and an output suitable for driving signal detection circuitry in a radio receiver. The circuit operates at the receiver intermediate frequency. A gain controlled cascode amplifier drives one input of a high gain differential amplifier. The other input is returned to a reference potential. A pair of current mirrors are coupled into the differential amplifier to provide a pair of single ended outputs. One output drives a peak rectifying diode to operate the automatic gain control and the other output drives a signal detection circuit. The current mirrors are ratioed so that the automatic gain control threshold is a predetermined fixed multiple of the signal threshold.