Abstract: A common electrical bus for coupling a plurality of units in a data processing system for the transfer of information therebetween. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time.

Abstract: A power supply provides a low-level DC voltage to DC load circuits by first rectifying the standard AC voltage and thereafter reducing the rectified AC voltage to the low-level DC voltage. The reduction of the rectified AC voltage to the low-level DC voltage is accomplished by a power transformer which is switched on or off by a pair of switching transistors. The switching transistors are operated in a "push-pull" mode by a pair of control transformers operating in combination with a control circuit. The control circuit produces various pulse conditions in the control transformers which turn their respective switching transistors on and off in a prescribed manner. An overcurrent sensing and control device prevents damage to components.

Abstract: In a data processing system employing paging and segmentation for storing information in memory, the input-output unit is provided with addressing capability for addressing and accessing memory without the intervention of the central processing unit. Page tables are set up in memory containing page table words, and a page table is assigned to each peripheral. A peripheral control word assigned to each peripheral includes a pointer to the start of the peripheral's page table whereby the peripheral through the I/O unit can locate its assigned page table, and page table words therein are combined with other control words to access paged memory locations.In one mode of operation an extended addressing mechanism is provided which allows the generation of absolute addresses of paged memory locations having an address field larger than the address field of the control words used to access such paged memory locations.

Abstract: Method and apparatus are disclosed for the serial transfer of data in a clockless manner. Data is transmitted in the form of signal state changes from a dispatcher to a receptor. The receptor is operative to translate the signal state changes into data and thereafter signal the data dispatcher that it has done so. The dispatcher is operative to transmit the next piece of data only after it has been appropriately signalled by the receptor.In accordance with another aspect of the invention, the dispatcher is capable of notifying the receptor when an end to the transmittal of data has occurred. The data receptor does not signal the dispatcher for further data when this occurs. The receptor instead signals a data sink that the previously transmitted data is available for copying. The data sink copies the data and thereafter authorizes the receptor to initiate further data receiving operations.

Abstract: A power supply provides a low-level DC voltage to DC load circuits by first rectifying the standard AC voltage and thereafter reducing the rectified AC voltage to the low-level DC voltage. The reduction of the rectified AC voltage to the low-level DC voltage is accomplished by a power transformer which is switched on or off by a pair of switching transistors. The switching transistors are operated in a "push-pull" mode by a pair of control transformers operating in combination with a control circuit. The control circuit produces various pulse conditions in the control transformers which turn their respective switching transistors on and off in a prescribed manner. An overcurrent sensing and control device prevents damage to components. The power on/fail circuit signals the load as to the status of the regulated load voltage and guarantees power for orderly shutdown after an input power outage.

Abstract: A program switching monitor is provided with means for preventing a central processing unit operating under control of a first program from switching to another program until certain conditions are met. Upon receipt of indications or data representative of the fact that all commands issued while the unit was operating under the control of the first program have been accounted for, program switching is permitted.

Abstract: A charge-coupled device (CCD) for amplifying and accumulating charge comprises a first CCD line, a plurality of time-independent CCD charge amplifiers each having an input gate connected to a surface potential tap on a respective one of the charge storage regions of the first CCD line, and a second CCD line for accumulating the charge which has been amplified by the charge amplifiers. The device permits the coherent accumulation of the charge in a time-independent manner. Arithmetic, logic, and complex signal processing functions may be conducted by suitable configurations of the charge amplifiers.

Abstract: Today's cathode ray tube oscilloscopes are widely used throughout the world and form an important basic tool in many industries. An apparatus to modulate the cathode ray display intensity, thereby enhancing the oscilloscope's capabilities in that it can now make more accurate measurements and, in effect, increase its band width, is disclosed. The apparatus to facilitate this effect is light weight, low cost, and easily connected to almost all oscilloscopes now in use.

Abstract: An input/output processing system comprises a number of modules including at least a pair of processing units connected to operate as a logical pair and a system interface unit having a number of ports. Each port connects to a different one of the modules for interconnecting pairs of modules for communication over a number of switching circuit networks included in the system interface unit. The system interface unit further includes control logic circuits for disconnecting each processor of the logical pair preventing the disconnected processing unit from communicating with other modules. The control logic circuits further include circuits which in response to special commands from a good processor are operative to condition via a special line, circuits in the disconnected processing unit to apply status signals representative of the contents of a control register to the system interface unit.

Abstract: An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted.

Abstract: A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system by eliminating a ROM address register for addressing microwords. The method or apparatus incorporates the use of a predetermined bit position in the microinstruction word which is set to a binary one when the microword is the last microword of an executing microprogram. The apparatus is responsive to the electronic representation of the binary one signal to cause the microinstruction execution sequence to branch to a predetermined location in the microprogram memory for execution of the following microinstruction; thus eliminating one ROM address register and at least one step in returning to a common address for starting the execution of another microprogram.

Abstract: Two numbers are multiplied together without first changing either of them, if negative, to a positive number, thereby minimizing the time required in the multiplication process. In the multiplication, depending upon the sign of the multiplier and the sign of a bit in a predetermined bit location of the multiplier as shifted in a shift register, the multiplier and the multiplicand are operated on by either a shift operation or operated on by a shift and add operation.

Abstract: A system and method for providing a control store arrangement in which a single memory having a plurality of memory locations can be used for storing sequences of microinstructions or scratch pad information. The number of storage locations defining the scratch pad area can be increased or decreased as required by assigning tag addresses to a desired number of scratch pad storage locations when the microinstruction routines are being assembled. In this manner, the locations defining the scratch pad areas can be tailored to the particular system operation to be performed. This eliminates the need for modifying the control store circuits to change the size of the control store scratch pad area.

Abstract: An input/output system includes a local memory module including a cache store and a backing store. The system includes a plurality of command modules and a system interface unit having a plurality of ports, each connected to a different one of the command modules and to the local memory module. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. The local memory module includes apparatus operative in response to each memory command to enable the command module to write into cache store the data which is requested to be written into backing store when it is established that such data has been previously stored in cache store.

Abstract: A processing unit includes emulation apparatus which operates to execute instructions of a target system, one of a plurality of ways depending upon the options and features of the target system being emulated. The options, features and characteristics of the target system for which the program was originated is defined by the different bits of an option mask word stored within the emulation apparatus. Initially, upon switching to an emulation mode of operation, the emulation apparatus under microprogram control is operative to store signal representations of the option mask word in one of its storage registers. The signals from the stored option mask word are applied to different portions of the emulation apparatus for conditioning the apparatus to execute target system program instructions in accordance with the structural characteristics of the target system for which the program was originated.

Abstract: A memory system includes a cache store and a backing store. The cache store provides fast access to blocks of information previously fetched from the backing store in response to commands. The backing store includes error detection and correction apparatus for detecting and correcting errors in the information read from backing store during a backing store cycle of operation. The cache store includes parity generation circuits which generate check bits for the addresses to be written into a directory associated therewith. Additionally, the cache store includes parity check circuits for detecting errors in the addresses and information read from the cache store during a read cycle of operation. The memory system further includes control apparatus for enabling for operation, the backing store and cache store in response to the commands. The control apparatus includes circuits which couples to the parity check circuits.

Abstract: A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an "ear" are as follows:A. when the process state switches from a running state to a waiting state; orB. when the process state switches from a running state to a suspended state.In both instances the CPU is given away and replaced by the PCB.

Abstract: A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows:1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU);2. ready -- the process is ready to run as soon as it is given control of the CPU;3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state;4. Suspended -- the process has been temporarily stopped (from a source external to the process).The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Abstract: A current mode arithmetic logic circuit utilizes a unique combination of a 4-bit and a 5-bit arithmetic logic unit for performing parity prediction and parity checking on an n-bit byte plus parity, in addition to performing 16 binary or 16 Boolean operations on two n-bit plus parity bytes.

Abstract: An electronic computer includes a plurality of printed circuit boards that are slideably mounted in spaced parallel planes within a housing. The housing contains an input/output bus arrangement which is substantially open in the middle. A power supply is detachably mounted to the housing in such a manner as to automatically connect to the input/output bus arrangement when it is secured in place. The power supply includes suction fans which draw ambient air in through the front of the housing over the printed circuit boards, through the open portion of the bus arrangement and hence over critical portions of the power supply. The air is initially drawn through perforated openings in a hinged control panel in one preferred embodiment. In another preferred embodiment, the air is drawn through a stationary member at the front of the housing.