Abstract: The invention comprises a CCD memory chip. A CCD chip is comprised of a plurality of arrays, each of which is in turn comprised of a plurality of CCD registers. A serial addressing system may be used to determine which of the arrays is accessed. Fault-tolerance with respect to defective arrays is achieved by the combination of having only the address circuits for properly functioning arrays form the bits of an N-bit addressing shift register, (whereas the address circuits for improperly functioning arrays are shorted such that they do not form a bit of the N-bit address shift register,) and disabling the voltage delivered to a faulty array. The control circuitry includes the address circuitry and further includes means for controllably providing power to the array components. A plurality of arrays comprises a chip having pads for connecting the chip to the rest of the system.

Abstract: Interface circuitry for a charged coupled device (CCD) register system. The circuitry enables a PARTIAL-WRITE mode of operation on a CCD storage register. A data bus, which may be bi-directional, is coupled to the sense amplifier of the CCD storage register. The coupling is via interface circuitry responsive to control signals for enabling the register and also enabling a WRITE operation. Discontinuation of the WRITE signals frees the data bus for other uses, thereby allowing for a PARTIAL-WRITE mode of operation. The interface circuitry is simplified so as to require a minimum of space, thereby enhancing the density characteristics of the CCD storage system.

Abstract: An apparatus and method for electrographically printing on a dielectric paper and transferring a toned image from the dielectric paper to plain paper. The dielectric paper receives an electrically charged latent image from an electrode device. The latent image is developed by applying a liquid or dry toner. The toned image on the dielectric paper is transferred onto the plain paper by conveying the dielectric paper and the plain paper together through a pair of conductive rollers. The dielectric paper is dried, fusing the residual image on its surface. The dielectric paper is then reused. The plain paper with the transfer image is dried, cut, and stacked.

Abstract: A data processing system having a plurality of interrupt sources coupled to provide interrupt handling of a process currently executing at a specified interrupt level. A level change signal which may be generated by the process itself may change the specified level of such process to another level which may make such process less interruptable to other interrupt sources. The level change provided takes place without interrupting the execution of such process.

Abstract: The invention discloses basic current mode logic (CML) circuits which function as feedback latches. One embodiment of the latch is a circuit for storing an input data signal. An alternative embodiment of the latch is a circuit which performs an And/Or function on a plurality of input data signals and then stores the result. The latch embodiments may be combined to form register systems. One combination of latch circuit provides a basic component for a shift register wherein a simple clocking system is utilized to provide a built-in delay mechanism required for proper operation of the shift register.

Abstract: In an associative memory, each cell 20 (FIG. 2) includes a recirculatory shift register 30 in which information is stored, a comparator 31 for comparing the stored information with a key fed on line 22, a gate 32 for passing the results of the comparison only in a key field defined by key field signals on line 23, and a flip-flop 33 which is set to 1 if the comparison fails. Flip-flop 33 controls reading from the cell. A flip-flop 37 is used to record whether the cell is full or empty, and a compare chain 40a, 40b passing through all cells in sequence is energized onwards from the first cell in which comparison is successful.A further development permits sequential retrieval and searching for the next key above a desired key if the desired key itself is not in the memory.

Abstract: A microprogrammed control for a controller operates with an instruction set which includes a pair of microinstructions, each having an op code field. One of the microinstructions has an op code field coded to specify a load constant operation in which a constant field of the microinstruction is loaded into an auxiliary register coupled to the control store of the microprogrammed control. The other microinstruction has an op code field coded to specify an unconditional return branch operation to a location specified by the contents of the auxiliary register loaded previously. Pairs of these microinstructions arranged in a predetermined sequence are included within each routine of microinstructions stored in the control store which the controller is required to execute in parallel.

Abstract: A microprogrammed peripheral controller in response to a command executes a sequence of microprogram routines stored in a read only memory normally provided for execution of peripheral control commands, based upon the state of various status indicators included in the peripheral controller. The controller automatically executes only those microprogram routines required to accomplish a given operation in the correct sequence by employing operation phase code bits stored in a scratch pad memory. The code bits are updated after execution of each microprogram routine and upon being changed to a predetermined state signal the controller when the given operation has been completed.

Abstract: A peripheral interface system connects a peripheral control unit (PCU) which controls a plurality of input/output devices having different data byte transfer rates with an input/output controller (IOC) of a data processing system. (A byte as used herein is defined as a desired predetermined number of bits, typically seven to 10 bits, although it could be one bit). When the byte transfer rate is less than the maximum asynchronous byte transfer rate of the interface system, the system operates in a first mode in which transfers of bytes of information by the data processing system are controlled to be in synchronism with the energization and deenergization of a pair of strobe control lines of the interface system. When the transfer of bytes is to exceed the maximum asynchronous byte transfer rate of the interface system, the IOC conditions the interface to operate in a second mode established by an additional pair of control lines.

Abstract: A data processing system includes a control unit, working store and an operating section for performing operations upon information fetched from the working store. The operating section includes a plurality of independent, functionally different units. The control unit during the fetching and execution of program instructions enables a number of the units to perform different operations simultaneously upon the same information thereby increasing the overall speed of processing program instructions.

Abstract: An electrographic printer is provided with a multiple row electrode structure wherein the electrodes in each row are mutually spaced one from the other and the electrodes of successive rows are staggered with respect to one another. The electrodes are each characterized by being of a smaller dimension in the direction of movement of the print medium than in the transverse direction, and an electrode drive circuit operates to maintain the electrodes activated when the print medium is moved across it to produce a latent image on the print medium.

Abstract: In a tape drive capable of utilizing various types of magnetic tapes and encoding techniques, there is provided a system of optimally controlling read/write operations under various sets of conditions. Logic circuitry is provided to respond to tape detection means and to pre-selected conditions and/or requirements, and to select electronic circuits either singly or in combination which provide optimum read/write operation for the set of conditions then obtaining.

Abstract: Computer addressing hardware and a method of address development which utilizes the concept of a segment as the unit of addressability is disclosed.The fundamental vehicle for addressing is the segment wherein an address space is defined for a process and is included as part of the controlled information of the logical processor (the collection of hardware resources and control information necessary for the execution of a process.) The address space defines a predetermined number of different segments in which instructions can access operands. Within a segment, access is by relative location to the beginning of the segment, and is computed during address development. Any attempt to access information beyond the upper bound of the segment is detected by hardware and an exception condition occurs.

Abstract: A coding method and apparatus that supports bidirectional scanning is disclosed for sequences of fields of variable length and/or type. Symmetric difference separators of the two immediately adjacent data field types are generated by exclusive-OR addition and utilized as punctuation marks to support bidirectional scanning. Parity checking techniques and hardware are utilized to resolve boundary alignment problems when a separator is in error. An extension of the concept of the invention to hierarchical parenthesized structures permit skipping over subtrees without scanning their contents.

Abstract: A method and apparatus are disclosed for monitoring the accuracy of electronic data transmitted over a communication channel or telemetry link. Data is monitored at the transmitting point and also at the receiving point. Data monitored at the receiving point is transmitted to the data transmitting station and then compared with the data monitored at the transmitting point. Means are provided to synchronize the data monitored at two points, so that comparison is conducted over the same monitored data. After synchronization the bit error rate (BER) is calculated based on the number of miscompares that result for a given quantity of data transmitted. When the system exceeds a predetermined level corrective action is taken.