Abstract: A digital television receiver includes a first phase locked loop which develops a sampling clock signal that is locked to the horizontal line synchronizing signals components of a composite video signal. A second digital phase locked loop is clocked by the sampling clock signal and develops a digital signal that is phase locked to the color burst signal. This signal is used as a regenerated color subcarrier signal to synchronously demodulate the chrominance components of the composite video signal into I and Q color difference signals. To compensate for frequency instabilities in the regenerated subcarrier signal caused by frequency instabilities in the line-locked clock signal, a third digital phase locked loop develops an oscillatory signal which is phase locked to a reference signal generated by a crystal controlled oscillator. Control signals from the third phase locked loop are applied to circuitry which develops control signal that is independent of the crystal frequency.

Abstract: A data display video monitor includes an automatic kinescope bias (AKB) control system for the type wherein kinescope cathode output pulses representative of the black current level conducted by the kinescope are produced in response to energizing the kinescope grid during sensing intervals. As a result of this operation, plural horizontal lines along the top edge of the visible display screen area are illuminated. To reduce the visible effect of the illuminated lines, the AKB system is activated for short sensing intervals (e.g., two seconds or less) between considerably longer holding intervals (e.g., five minutes).

Abstract: An arrangement is provided for computing the magnitude value of the vector sum of two quadrature-related component signals I and Q with a minimal of hardware. To this end, the magnitude values of the orthogonal I and Q signals are applied to a ROM as address codes to produce the Log.sub.B .vertline.I.vertline. and Log.sub.B .vertline.Q.vertline. values to the logarithmic base B. The smaller of the Log.sub.B .vertline.I.vertline. and Log.sub.B .vertline.Q.vertline. logarithmic values is subtracted from the larger of the logarithmic values to produce the absolute value .vertline.D.vertline. of the difference between the respective logarithmic values. The difference value D is applied to a ROM as an address code which is programmed to generate a correction value F=0.5 Log.sub.B (1+B.sup.-2.vertline.D.vertline.).

Abstract: A television receiver includes an audio signal processing arrangement for expanding a second audio program (SAP) signal compressed in accordance with the "dbx" system in a relatively simple manner. The signal processing arrangement includes a first filter for providing a first amount of deemphasis. A controllable gain amplifier has its input coupled to the filter and its gain controlled by a filtered signal representative of its input signal. A second filter at the amplifier output provides a second amount of deemphasis.

Abstract: A television receiver which includes an automatic deghosting system synchronously demodulates IF television signals to generate baseband signals representing the in-phase and quadrature phase modulation components of the IF signals. A signal representing the phase difference between the carrier of the signal as broadcast and the carrier of the received signal, which may include ghosts, is generated from the in-phase and quadrature signals. This signal is applied to circuitry which develops signals proportional to the sine and cosine of the phase angle separating the broadcast carrier phase and the received carrier phase. The demodulated in-phase and quadrature phase baseband signals are multiplied by the sine and cosine signals in a complex multiplier to correct distortion resulting from the synchronous demodulation using the carrier of the received signal.

Abstract: A digital television signal deghosting system includes an IIR filter responsive to the in-phase and quadrature-phase components of modulated television signals for cancelling ghost signals irrespective of their phase. A double-conversion tuner develops modulated composite video signals having a 3f.sub.c carrier frequency. An analog-to-digital converter responsive to a two-phase 3f.sub.c clock signal develops digital samples which alternately represent the baseband in-phase and quadrature-phase components of the modulated video signals. These samples are separated to develop digital signals representing the in-phase and quadrature-phase components of the modulated television signals.

Abstract: An automatic deghosting system synchronously demodulates IF television signals to generate baseband composite video signals. A strong RF ghost signal having a carrier phase that differs from that of the desired signal may cause demodulation phase errors, causing quadrature distortion in the baseband video signals. The circuitry shown in this disclosure synchronously demodulates the quadrature component of the IF television signals and develops a signal proportional to the difference between the values of the baseband quadrature signal immediately before and immediately after the leading edge of the vertical sync pulse. This signal, which is proportional to the demodulation phase error, is used to control a phase locked loop that regenerates the in-phase and quadrature carrier signals used by the synchronous demodulators to substantially eliminate any demodulation phase error.

Abstract: A digital television receiver, having a line-locked clock, includes a partly digital, partly analog phase locked loop. This phase locked loop regenerates two quadrature phase related subcarrier signals that are used to synchronously demodulate the chrominance signal components of the composite video signals into two color informaiton signals. The phase locked loop includes an analog voltage controlled oscillator which generates a signal that is independent of any frequency instability in the line locked clock signal. An analog-to-digital converter digitizes this signal to provide one of the subcarrier signals. This subcarrier signal is applied to a read-only memory to generate the second subcarrier signal. The two color information signals are obtained by multiplying the chrominance signals by the first and second subcarrier signals.

Abstract: A slow motion system includes a variable interlace constant line-rate video camera, a variable speed recorder and a line-rate converter connected in cascade. During slow motion shooting the camera interlace ratio is increased, the recorder playback speed is reduced by the interlace ratio and the converter increases the line-rate of the recorded signal in proportion to the interlace ratio thereby providing a constant field-rate constant line-rate video output signal having a temporal resolution which increases as the interlace ratio increases.

Abstract: Apparatus for estimating noise in an electrical signal having substantially redundant recurring intervals includes circuitry for producing difference samples corresponding to signal differences between the recurring redundant intervals. A number of difference samples are averaged, and ones of the difference samples contributing to each average are subtracted from the averages. Magnitude values are extracted from the differences between the averages and the difference samples. A predetermined number of the magnitude values are averaged to produce a noise estimate signal.

Abstract: A frame comb type composite video decoder which does not require motion adaptive processing circuitry generates low frequency luminance signal components from one field of composite video signal. The high frequency luminance component is derived from two lines of composite video signal from each of two fields disposed before and after the field from which the low frequency luminance signals is developed.

Abstract: A binary subtracter stage for subtracting single bit binary numbers includes a first exclusive OR gate to which the numbers to be subtracted are applied. The output of the exclusive OR gate is connected to one input of a second exclusive OR gate which has a second input connected to a borrow input signal. The output of the second exclusive OR gate provides the difference between the single bit binary numbers. A borrow output signal is generated with the combination of a pass transistor coupled between the borrow input and borrow output terminals and a three state logic circuit which has its output termial connected to the borrow output terminal. The pass transistor is controlled by the output of the first exclusive OR gate and the three state logic circuit is controlled by the single bit binary numbers to be subtracted.

Abstract: A solid-state imager for a television camera which generates a compatible wide-screen signal, i.e., a wide-screen signal with compressed left and right edge portions for each television line. The solid-state imager includes photosensitive picture elements (pixels) which are nonuniformly distributed in each row of the imager in accordance with the amount of compression desired in the left and right edge portions of the signal.

Abstract: In a wideband video signal processing system, a video signal is capacitively coupled to a kinescope via a signal path. A video signal clamping diode is coupled from the video signal path to a low impedance point in a feedback path of a keyed switching transistor. Parasitic capacitances associated with the clamping diode and with the output of the switching transistor are decoupled from the video signal path by means of a first decoupling resistor, and a second decoupling resistor included in the feedback path, respectively.

Abstract: A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce visual artifacts in the displayed image due to clock skew relative to sync when non-standard video signals are processed. The skew errors are corrected by circuitry which measures the skew of the read and write clocks and delays the video signal as a function of a difference between the clock skew measurements.

Abstract: A television receiver includes apparatus for stabilizing an on-screen character display by which the deflection signal source is controlled for operating in a free-running mode, substantially unaffected by signal variations on the sync input line, rather than in a synchronized mode when sync is unreliable or otherwise undesirable. As another feature, the deflection signal source is caused to operate at substantially the same frequency in either mode.

Abstract: In a luminance channel of a color television receiver, a luminance signal is conveyed to the input of a delay line via first and second series connected source resistors. A series tuned trap tuned to the chrominance subcarrier frequency is coupled between the junction of the first and second resistors and a point of reference potential. The coaction of the first and second source resistors and the trap results in a significant reduction in frequency dependent source impedance variations at the input of the delay line.

Abstract: The line rate of a video input signal is doubled for display in progressive scan fashion by dual mode processor which generates added lines for the display by interpolation when displaying normal television pictures and by replication (repeating lines) when displaying characters. The processor mode is automatically controlled by an image analyzer which identifies fields of text by counting "major" transitions of the video input signal occurring within a field and comparing the count with a threshold value. Errors in identification are minimized by a further counter which integrates the field count and a hysteresis detector which controls the processor operating mode in accordance with high and low limits of the integrated field count.

Abstract: A video signal processing and display system includes apparatus for automatically controlling the bias of an image display device. A sample and hold network of the control apparatus includes an amplifier, a switch and a storage capacitor. During sampling intervals the switch connects the capacitor directly to a bias control terminal. During substantially longer holding intervals, the switch connects the capacitor to the bias control terminal via the amplifier.

Abstract: A progressive scan receiver includes a frame interpolation filter for generating added lines for display in a given field from a video input signal by interpolation from corresponding elements of immediately preceding and following fields. A second filter provides a line interpolated signal having picture elements spatially and temporally coincident with corresponding elements of the frame interpolated signal and having a suppressed vertical detail component. A third filter attenuates the vertical detail component of the frame interpolated signal. An output circuit combines the signals of the three filters to provide a frame interpolated video output signal in which the vertical resolution of the video input signal is preserved and motion artifacts characteristic of frame interpolation are attenuated.