Abstract: A speed-up memory converts interlaced RGB input signals to double line-rate (progressive scan) form. A vertical detail signal is derived from the RGB input signals before or after speed-up and a vertical peaking signal is derived from the detail signal. During the first read operation of the speed-up memory both signals are added to the speeded-up signals to effect a preshoot of the resultant signal and during the second speed-up memory read operation only the peaking signal added to affect an overshoot of the resultant signals whereby alternate lines of the converted RGB signals exhibit enhanced vertical detail.

Abstract: In a television receiver, a non-saturating kinescope driver amplifier arrangement includes an input current limiter circuit coupled between a source of video signal and a current responsive signal input of a feedback kinescope driver amplifier. The limiter circuit, e.g., including a diode limiter, limits the magnitude of input signal currents applied to the current input of the amplifier to prevent the amplifier from exhibiting a saturated conductive state.

Abstract: A motion detector for detecting the occurrence of image changes between successive fields of video information includes a signal averager for averaging the video signal from two lines of video signal of one video field and a signal averager for averaging the video signal from three lines of video signal of a successive field. The two average video signals are coupled to comparing means which develops a motion indicating signal when the two average video signals differ.

Abstract: A video signal processing system which employs a frame memory having a single output is operated to provide both field and frame delayed signals. The frame memory is operated in a serial mode at twice the video signal sample rate. Video samples are input to the memory on alternate stages and alternate samples output from the memory are routed back into the vacant memory stages. Alternate samples output from the frame memory correspond to field and frame delayed samples.

Abstract: System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses.

Abstract: An interline comb filter for separating luminance signal from composite video includes a subcarrier trap which is selectively engaged in the comb filtered luminance signal path to remove "hanging dots". Control for the subcarrier trap is provided from vertical detail signals.

Abstract: A phase locked loop system is described in the context of a digital television receiver. The system includes a band-pass filter which shifts the phase of burst samples provided to it by 33.degree.. This phase shift makes the zero-crossing points of the filtered burst signal coincident with the I color difference signal sampling phase relative to the unfiltered burst signal. The phase locked loop uses a zero-crossing phase detector to develop a control signal for a VCO. The oscillatory signal provided by the VCO has a frequency of, for example, four times the frequency of the burst, but shifted in phase relative to the burst to allow sampling composite video signal coincident with the phase of at least one of the I and Q color difference signals.

Abstract: A field comb filter for separating luminance signal from NTSC composite video additively combines signals separated by 263 horizontal lines. Vertical detail is restored and motion compensation provided by subtractively combining signal separated by 262 horizontal lines and adding the difference to the separated luminance signal.

Abstract: Comb filtered video signals having reduced artifacts are adaptively produced by circuitry including delay elements for providing a plurality of video signals delayed by integral numbers of horizontal line periods, for example, signals delayed 1H, 2H, 1 field, 1 frame, etc. Signals from pairs of these lines of signals are compared by developing the sums of cross differences of samples spanning the sample point to be filtered to produce a signal indicative of the pairs of lines having the highest degree of signal correlation at that instant. The pair of lines exhibiting highest correlation are selectively applied to signal combining circuits to generate comb filtered luminance and chrominance signals in the conventional manner.

Abstract: An automatic gain control (AGC) circuit is described in the context of a phase locking system in a digital television receiver. The signal produced by the phase locking system is used to develop a sampling clock signal that is locked in frequency and phase to the color reference burst signal component of a color television signal. An AGC detector develops a gain control signal by averaging only those samples which would correspond to the peaks of the burst signal if the sampling clock signal were locked to the burst signal. The gain control signal is applied to a multiplier which increases or decreases the magnitude of the television signal samples to bring the calculated peak amplitude value of the burst signal within a predetermined range. The AGC circuitry interacts with the phase locking system to decrease the lock-up time when there is a relatively large difference in phase between the burst signal and the sampling clock signal.

Abstract: A DC coupled system for automatically controlling the peaking content of a video signal includes a frequency selective peaking amplifier, a source of control voltage for controlling the conduction of the amplifier, and an interface circuit including a high output impedance current source network for coupling the control voltage to the amplifier. The interface circuit prevents the amplifier from being loaded excessively by the impedance of the source of control voltage, and assists to assure that the amplifier exhibits negligible gain for DC conditions.

Abstract: Circuitry for detecting nonstandard video signals is disclosed. This circuitry is used in a sampled data video signal processing system to control signal processing steps which utilize a frame store memory. The detecting circuitry includes a programmable counter which generates a standard horizontal pulse signal having a 70 ns pulse width by counting down a sampling clock signal that has a frequency proportional to the color subcarrier frequency of the video signals. The circuitry generates another horizontal pulse signal having a pulse width of less than 140 ns from the horizontal sync pulses of the input video signals. These pulse signals are compared in a coincidence detector which produces a signal that is in a first state when the pulses of the two signals overlap at least once in every twenty-five horizontal line times and in a second state otherwise.

Abstract: A chroma overload system includes an up/down counter to develop a chroma gain/attenuation signal. Overload conditions are detected and responsive thereto pulses are generated to cause the counter to decrease chroma gain. In the absence of overload conditions, a pulse generator conditions the up/down counter to increase chroma gain to a predetermined limit. ACC is incorporated by monitoring burst and establishing the counting range and thereby the range of gain developed by the up/down counter.

Abstract: A television receiver with a planar faceplate kinescope includes an automatic kinescope bias (AKB) control system wherein the kinescope electron gun is energized to induce a cathode output current, representative of the kinescope black image current level, in response to an auxiliary drive signal applied to the electron gun during AKB operating intervals. The auxiliary signal exhibits an amplitude for inducing the cathode current only during horizontal trace intervals encompassed by the interval when the auxiliary signal occurrs.

Abstract: In a digital video signal processing system including an image reproducing kinescope and a digital-to-analog converter (DAC), excessive kinescope beam current are automatically limited in response to a control signal which varies a reference voltage for the DAC such that the peak-to-peak amplitude of analog video signals from the DAC is reduced. A version of the control signal is applied to the output of the DAC with a magnitude and polarity for substantially negating unwanted shifts of the video signal black level during the beam current limiting mode.

Abstract: A phase detector included in a digital television receiver develops first and second phase error signals based on samples of the color reference burst signal taken from one and two horizontal lines respectively. The first phase error signal is used to attain coarse synchronization between a sampling clock signal and the burst signal. The second phase error signal is used to enhance synchronization accuracy after coarse synchronization has been attained.

Abstract: A television system for generating a composite video signal for an image having extended aspect ratio such as 5:3, and for displaying such composite video signal in a television image area having the same extended aspect ratio. The horizontal blanking interval of an NTSC composite video signal is utilized for the transmission of video information characterizing either the right or the left edge of a display line of the picture; whereas, the remaining portion of the NTSC signal is utilized for the transmission of video information characterizing the inner portion of the display line between the edges. The video information for the missing edge in each display line is derived in the receiver from video edge information of adjacent display lines.

Abstract: In a television receiver including a kinescope, a kinescope driver stage includes a video amplifier with an associated feedback path. A first emitter follower transistor couples amplified video signals from the amplifier output to the kinescope. A second emitter follower transistor, included in the feedback path for maintaining the continuity thereof, couples amplified video signals to the kinescope when a normally nonconductive diode coupled between the outputs of the emitter follower transistors is rendered conductive in the presence of large video signal amplitude transitions sufficient to render the first follower transistor nonconductive.

Abstract: A video monitor includes an image displaying kinescope which exhibits a temperature dependent conduction characteristic that results in declining light output and image brightness during an initial warm-up period, from a time soon after the system is initially energized to a time several minutes later when steady-state operation is reached. To counteract the declining kinescope light output during the warm-up interval, a compensation circuit having a time constant characteristic which approximates the kinescope conduction characteristic during the warm-up interval causes the kinescope to exhibit increasing light output and image brightness during the warm-up interval. Thus substantially uniform light output is produced over the warm-up interval.

Abstract: A double scanning receiver includes a video speed-up memory with read and write clocks locked to multiples of burst. Visible artifacts tend to be produced when displaying non-standard video signals (e.g., from a VCR, game, computer, etc.) due to skew of the memory clock signals with respect to horizontal sync. Skew artifacts are corrected by delaying the output signal of the memory as a direct function of the read clock skew and as an inverse function of the write clock skew. The write clock skew is measured for each memory read and write cycle. The read clock skew for the first memory read cycle is obtained by doubling the write clock skew measured at the start of the first read cycle. The read clock skew for the second memory read cycle is obtained by adding the write clock skew measured at the start of the second read cycle to a measured half-period of the video input signal and doubling the fractional part of the sum thereof.