Abstract: A method (600) and simulation tool (200) having enhanced accuracy and speed for simulation using ray launching in a mixed environment (20) by using adaptive ray expansion mechanisms can include a memory (204) coupled to a processor (202). The processor can select (602) a target area within the mixed environment and modify (604) the propagation properties of the adaptive ray expansion mechanisms according to characteristics classified for the target area. The processor can further classify characteristics for the target area by transmitting and reflecting rays for indoor building regions and for outdoor building regions. The number of bounces or a power level threshold assigned to a transmitted ray is a function of the environment where it propagates. The simulation tool can determine the target area or a region of interest by using a global positioning service device (230) externally attached to a device performing functions of the simulation tool.

Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Abstract: A method (100) in a multi-transmitter mobile device (201) can include transmitting (102) a signal in a first mode causing an interrupting signal to a transmission in a second mode, receiving (104) commands to increase power in the second mode as a result of the interrupting signal, and circumventing (106) the commands to increase power in the second mode when transmitting the signal in the first mode interrupts the signal in the second mode. The method can circumvent commands to increase power by alternating (108) a power control bit up and down and masking a true bit coming from a base station to the multi-transmitter mobile device. In another alternative, the method can circumvent by storing (110) a power control setting prior to the interrupting signal with a stored value, waiting for a removal of the interrupting signal, and overwriting a calculated power control setting with the stored value.

Abstract: A modified housing in a portable product (400, 500, 700, or 800) includes a housing detail (405, 506, 706 or 710 or 806) forming at least a portion of a loud speaker back cavity having a pipe inner diameter for a resonant pipe (408, 508, 708, or 808), and a modification to the housing detail altering a cross section area of the pipe inner diameter to compensate for changes to a loud speaker back cavity volume. The housing detail can include a battery door (404, 504, 704) for the portable product that forms at least one side of the resonant pipe. The battery door can define the loud speaker back cavity volume and further fills at least part of the resonant pipe in a manner that maintains the loud speaker back cavity volume and the cross sectional area of the pipe inner diameter at a predetermined ratio.

Abstract: A scalable video compression system (100) having an encoder (120), bit extractor (140), and decoder (160) for efficiently encoding and decoding a scalable embedded bitstream (130) at different video resolution, framerate, and video quality levels is provided. Bits can be extracted in order of refinement layer (136), followed by temporal level (132), followed by spatial layer (134), wherein each bit extracted provides an incremental improvement in video decoding quality. Bit extraction can be truncated at a position in the embedded bitstream corresponding to a maximum refinement layer, a maximum temporal level, and a maximum spatial layer. For a given refinement layer, bits are extracted from all spatial layers in a lower temporal level prior to extracting bits from spatial layers in a higher temporal level for prioritizing coding gain to increase video decoding quality, and prior to moving to a next refinement layer.

Abstract: A multiband folded dipole transmission line antenna (300, 400, 500) including a plurality of concentric-like loops (210, 214, 508) where each loop comprises at least one transmission line element (204, 206) and at least a pair of folded dipole antenna elements (302, 304), a first connection point and a second connection point shared among the plurality of concentric-like loops, and a first inverted L antenna element (216) coupled to the first connection point and a second inverted L antenna element (218) coupled to the second connection point. Additional embodiments are disclosed.

Abstract: A system (100) and method (400) for improving Radio Frequency (RF) Antenna Simulation is provided. The method can include determining (402) a proximity of an antenna (250) to a scattering structure (210), determining (410) a switching distance to the scattering structure that establishes when to switch the antenna on (416) and off (418) from a composite antenna pattern to a free space antenna pattern, and predicting RF coverage of the antenna responsive to the switching. The switching distance can be a function of a material type and a surface geometry of the scattering structure and a wavelength of the antenna. The method can also include evaluating a sensory mismatch in the antenna, and using a composite antenna pattern corresponding to the sensory mismatch.

Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Abstract: A system and method of managing interrupt requests from IP cores within an integrated circuit design can include capturing environmental constraints within constraint files for the integrated circuit design (where the constraints can include information regarding a board upon which an integrated circuit device is mounted, pin locations for interrupt signals, and the sensitivity of the interrupt signals), generating connections among interrupt sources, interrupt controllers, and interrupt request ports on microprocessor cores within a device environment, and automatically instantiating controller logic when interrupt controllers are lacking during compilation of the device design. The method and system can also identify within the design, processor and bus interconnections as well as each interrupt port on the IP cores and the sensitivity requirements for each port which can be stored within description files for a corresponding IP core instead of an HDL specification.

Abstract: A multiband comformed-slotted-folded dipole antenna (200) having a unitary conformed shape conductor conforming to an internal communication device configuration (400). The antenna can include a folded dipole (203, 205, 209, 206, 204) forming a part of the unitary conformed shape and having a first portion (212 or 213) forming at least one slot in a slotted plane (220) and a second portion (210 or 211) forming at least one slot in a second plane (230) substantially perpendicular to the slotted plane. The at least one slot in the second plane controls high band antenna resonance and a length (209) of a metal portion in the slotted plane controls lower band resonance. Additional embodiments are disclosed.

Abstract: A system (170) and method (300) for ray launching is provided. The system can include a transmitter (110) for successively launching a plurality of rays, and a receiver (120) for receiving transmission rays and reflection rays. A controller (141) can be included for selectively adjusting an angular spacing and eliminating rays in successive launches to focus an energy on the receiver. A method (430) of terminating rays for reducing computational complexity is provided. A method (340) for ray weighting for increasing a computational speed of ray propagation is provided. In one aspect, a quality of service (108) can be determined at the receiver based on ray propagation.

Abstract: A method of input/output (I/O) block placement assigned to an input/output bank includes formulating a placement algorithm using integer linear programming (ILP) and simultaneously placing single groups and Relatively Placed Module (RPM) groups of I/O blocks in the I/O bank. The method further includes determining a placeability matrix P and a binary assignment matrix X used for the ILP. The method can further eliminate all assignment matrix elements of X equal to 0 in the integer linear programming and re-index any remaining elements. The method can further place all I/O blocks according to a solution if solving of the standard ILP formulation results in a feasible solution. Optionally, the method generates a placement solution that is as close as possible to an external reference solution specified by designer. Optionally, the method analyzes which constraints were violated and generates useful error information.

Abstract: An on-chip stuck-at fault detector in an integrated circuit using a test circuit for critical path testing can include a sequence circuit having a first sequential circuit and a second sequential circuit to sensitize the critical path between a source sequential circuit and a destination sequential circuit, an analyzer circuit for capturing an output from the destination sequential circuit and comparing a signal between the destination sequential circuit and the analyzer circuit at predetermined clock cycles, and a controller for strobing the analyzer circuit at the predetermined clock cycles. The first sequence and second circuits can both be initialized to a zero mode (e.g., x=0 and y=0). Thus, no stuck-at faults are determined if the destination sequential circuit and an analyzer sequential circuit in the analyzer circuit have different values and a zero result is captured at a sticky-bit flip flop.

Abstract: An arrangement and method of reducing power in bidirectional I/O ports includes driving an input signal from an I/O port by asserting a high impedance (Hi-Z) signal to an output drive, driving an output signal from the I/O port by refraining from asserting a Hi-Z signal to an output driver, and feeding back the output signal to an input driver when driving the output signal. The method can float the I/O port when the Hi-Z signal is asserted on the output driver or drive the I/O port as an input when the Hi-Z signal is asserted on the output driver. The method can refrain from floating a signal back into the I/O port when driving a signal out by driving a constant logical zero back into the I/O port or driving a constant logical one back or by maintaining a last value driven.

Abstract: A method (10) and system (200) for associating a user profile (39) to Caller ID signal can include a processor (202) that is controlled under an operating system allowing multiple profiles. The processor extract (12) Caller ID information from a Caller ID signal, associate (14) at least a portion of the Caller ID information with at least a predetermined profile stored on the wireless communication device, and enable (16) access to the predetermined profile only when the portion of the Caller ID information is associated with the predetermined profile stored on the wireless communication device. The method can store (18) separate profiles on the wireless communication device for each Caller ID or for each predetermined set of Caller IDs or store separate multiple profiles for each Caller ID or set of Caller IDs and further enable user selection among the multiple profiles.

Abstract: A fast linked multiprocessor network including a plurality of processing modules implemented on a field programmable gate array and a plurality of configurable uni-directional links coupled among at least two of the plurality processing modules provide a streaming communication channel between at least two of the plurality of processing modules. Such configuration provides a function accelerator that can feed at least one processor with data values using one custom instruction to put data values on at least one uni-directional serial link and that can extract data values from at least one processor using one custom instruction to get data values from the at least one uni-directional serial link.

Abstract: A system for securely using decryption keys during FPGA configuration includes a FPGA having a microcontroller for receiving a bitstream having an encrypted bitstream portion as well as a configuration boot program. The configuration boot program can be code that runs on an embedded hardware microcontroller or a software microcontroller. The system further includes a key storage register coupled to the microcontroller for storing key data from the microcontroller, a decryptor coupled to the key storage register, and a configuration data register in the FPGA. Preferably, only the decryptor can read from the key storage register and the configuration data register cannot be read by the microcontroller after the decryptor is used.

Abstract: A method (100) of translating an imperative language function into a parameterized hardware component can include the steps of using (102) formal imperative function arguments to represent at least one among a component input port and a component parameter and distinguishing (104) between formal imperative function arguments intended as component parameters from formal imperative function arguments intended as component input ports. The method can generate (106) hardware description by providing a framework where imperative language functions can be translated into hardware components by being instantiated, combined and simulated. Arbitrary code can be associated (108) to a function-importing block as parameterization code and enabling an assignment of arbitrary code to actual imperative function arguments. The arbitrary code can be executed (110) in an interpreter that analyzes assigned variables by name and compares variable names with the formal argument identifiers in an imported function.

Abstract: A portable electronic device includes a portable electronic device housing (110) where the housing has at least one orifice (120) to an internal portion (130) of the housing. The electronic device also includes a flex circuit (140) projecting from the orifice, a seal (150) located at the orifice to prevent liquid from entering the internal portion of the housing, where the seal has a first portion (150a) and a second portion (150b). The first portion and the second portion of the seal sandwich the flex circuit and the seal is snug fit in the orifice. A method (300) of installing a seal for a portable electronic device housing having an orifice through which a flex circuit protrudes is also provided.

Abstract: A method for customization of the software of an FPGA-based SoC includes the steps of selecting (380) a system component used for customizing the FPGA-based SoC, configuring (382) the selected system component with parameters for use with the FPGA-based SoC and propagating (384) the parameters used to configure the selected system component to peer system components. The method further includes the step of configuring (388) the peer system components using the propagated parameters during customization of the FPGA-based SoC and creating (401) a software interface to the selected system components and to the peer system components.