Abstract: A test circuit in an integrated circuit (200 or 300) is used for verifying a critical path of a circuit (230) under test. The test circuit can include a sequence generator (202) generating a data signal for the critical path, a source sequential circuit (208) for receiving the data signal coupled to an input of the critical path, a destination sequential circuit (210 or 310) for receiving an output of the critical path, and an analyzer circuit (212 or 312) for verification of timing of the critical path by measuring timing from the source sequential circuit to a clock enable pin (209) or a set/reset pin (309) of the destination sequential circuit. The test circuit can further include a controller circuit (220) for strobing a comparison circuit (218) in the analyzer circuit at a predetermined clock time. The integrated circuit can be part of an FPGA or FPGA fabric.

Abstract: A system and method of configuring a partially reconfigurable switch includes a pipelined partially reconfigurable switch interconnect may include a desired subset of connections in a switch interconnect, a partial bitstream defined for each of the desired subset of connections stored in a memory such as SRAM serving as a buffer, and a controller for cyclically applying the partial bitstream to the switch interconnect. The controller may determine a connection instance and duration for each client access of the switch interconnect in a synchronous manner. A clear to send (CTS), receive data (RD), destination address, and source address at each client may be sent with each partial bitstream for each desired subset of connections. The partially reconfigurable switch and a plurality of partially reconfigurable slot clients may be formed in a silicon backplane.

Abstract: The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based SoC can be configured using parameters that can be automatically propagated and used to configure peer system components. During configuration of the peer system components, other parameters used to configure those peer system components can also be propagated and used to configure other system components during customization of the FPGA-based SoC.

Abstract: A hardware stack (HSTACK) structure using programmable logic can include a look-up table (LUT) random access memory (RAM) circuit and circuitry within the LUT RAM circuit for propagating data upwards and downwards. The hardware structure can be arbitrarily assembled into a larger structure by adding stacks to a top portion, a bottom portion, or a portion between the top portion and the bottom portion. The hardware stack structure can further include a virtual stack (VSTACK) structure coupled to the HSTACK structure within a field programmable gate array (FPGA) fabric. The VSTACK can be arranged in the form of an appended peripheral memory and cache control for virtual extension to an HSTACK address space. The hardware stack structure can further include an auxiliary reset circuit.

Abstract: A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.

Abstract: An apparatus is disclosed for a multiband antenna (102) in a communication device (100). An apparatus that incorporates teachings of the present invention may include, for example, an antenna having a finite ground surface (201, 401), and an elongated conductor (206, 406) that is characterized by a length and is spaced from the finite ground surface. The elongated conductor has a first slot (208, 408) extending through a substantial portion of the length of the elongated conductor, and a second slot (210, 410) having a shorter length than the first slot. The antenna further has a grounding conductor (216, 416) coupling the finite ground surface to the elongated conductor, and a signal feed conductor (214, 414) coupling to the elongated conductor.

Abstract: A multiprocessor system (206) having a plurality of processors (304-306), each processor capable of processing at least one queue (404A-404N) of at least one service application, and at least one task (402A-402N) comprising at least one of the at least one queue; and wherein a first processor and a second processor of the plurality of processors is each programmed to delegate (602) a service application from the first processor to a queue of the at least one queue of the second processor, evaluate (604-606) the queue at the second processor according to flow control criteria, process (608) the service application at the second processor upon satisfying the flow control criteria, and reject (610) the service application at the second processor upon failing to satisfy the flow control criteria.

Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Abstract: A method (10) of reducing a size of a netlist for a target architecture can include the steps of creating (12) a netlist of objects for the target architecture, identifying (14) objects specific to the target architecture that are repeated regularly to identify potential dummy objects, creating (15) a list of objects used by a design in the target architecture, and forming (16) a list of unused objects in the target architecture from the netlist of objects and the list of objects used by the design. The method can further include the steps of replacing (18) at least one object in the list of unused objects with an appropriate dummy object to form a modified netlist and simulating (19) the modified netlist.

Abstract: A method (600) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device (605) and defining modules having components of a same type (615). A set of shapes associated with a module can be determined (610). The circuit design can be annealed (620) to determine a floorplan using the cost function and the set of shapes for the module.

Abstract: A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.

Abstract: A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.

Abstract: A method of performing analytical placement of components for a circuit design can include the steps of modifying an analytical formulation for placement of the circuit design a priori (when the circuit design or programmable device fabric includes inhomogeneous components) providing a modified analytical formulation and applying the modified analytical formulation during placement of the circuit design. The step of modifying can optionally include introducing terms into the analytical formulation that push components away from locations in which they cannot reside (such as a large hole in the programmable device fabric due to a large, fixed component such as a CPU core) or alternatively or optionally the step of introducing (115) terms into the analytical formulation that pull components that can only reside at a relatively small number of locations towards those locations.

Abstract: A receiver unit (400) capable of determining its approximate location using a first and a second satellite transmission source (12 & 14) and, a first terrestrial transmission source (18) includes a receiver (402) and decoder (450) for receiving and decoding a first synchronization pulse from the first satellite, a second synchronization pulse from the satellite signal, and a third synchronization pulse from the terrestrial source. The receiver unit further includes a counter (412) for measuring a first delay between the first synchronization pulse and the second synchronization pulse and for measuring a second delay between one of the first synchronization pulse or the second synchronization pulse and the third synchronization pulse. The receiver unit further includes a processor (421) for determining an east-west constant delay line based on the first delay and for determining a north-south constant delay line based on the second delay.

Abstract: A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each component of the local clock nets (520). The method further can include generating at least one cost function (530, 550) to evaluate (555) different placements of components of the local clock nets. The components (220, 240) of the local clock nets (205) can be annealed (535–575) using one or more of the cost functions to assign locations to each component of the local clock nets.

Abstract: A method of a rule-based operation can include the steps of dividing a design rule into at least one of three components including an application criteria, a rule condition, and an action. The method can further include the steps of expressing the design rule as a datafile or source code and binding the three components together to form a rule object at runtime.

Abstract: The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based SoC can be configured using parameters that can be automatically propagated and used to configure peer system components. During configuration of the peer system components, other parameters used to configure those peer system components can also be propagated and used to configure other system components during customization of the FPGA-based SoC.

Abstract: A method of physical design for a programmable logic device (PLD) can include associating movable objects of the PLD with a criticality measure that is dependent upon timing information for a configuration of the PLD (115). The method further can include calculating the criticality measure for each movable object (125) and calculating a probability for each movable object (130). The probability can depend upon the criticality measure for the movable object. The method also can include selecting one or more of the movable objects for controlled move generation within a simulated annealing process (135). Movable objects are selected for controlled move generation according to the probabilities assigned to the movable objects.

Abstract: A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.

Abstract: A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.