Abstract: One embodiment of the present invention provides a system that merges checkpoints on a processor. The system starts by executing instructions speculatively during a speculative-execution episode. The system then generates a first checkpoint and a second checkpoint during the speculative-execution episode. Next, the system merges the first checkpoint with the second checkpoint during the speculative-execution episode, wherein merging the first and second checkpoints conserves processor resources.

Abstract: One embodiment of the present invention provides a system that reduces the number of heap handles in a program. First, the system builds an intermediate representation of the program. The system then analyzes the intermediate representation to determine whether executing a function may cause a garbage-collection operation. If so, the system further analyzes the program to determine whether a heap handle in the program is defined and/or used in proximity to a call to the function. Next, the system determines whether the heap handle can be replaced by an ordinary pointer, in order to facilitate subsequently converting the heap handle to an ordinary pointer, if possible. Note that converting a heap handle to an ordinary pointer reduces the space requirements for the program and increases the speed and efficiency of the program and garbage collection operations.

Abstract: One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a wafer. When the photolithography process exposes the wafer to a layout, the wafer can include topography variations which were caused by previous exposure-and-development steps. The process model can be used to predict patterns that are created on the wafer when the wafer is exposed to a second layout, wherein the wafer includes topography variations that were caused by resist features that were created when the wafer was exposed to a first layout. The process model can include a first term and a second term, wherein the first term is convolved with a sum of the first layout and the second layout, and wherein the second term is convolved with the second layout.

Abstract: Transparent network devices intercept messages from non-transparent network devices that establish a connection. Transparent network devices modify these messages to establish an inner connection with each other. The transparent network devices mimic at least some of the outer connection messages to establish their inner connection. The mimicked messages and any optional reset messages are intercepted by the transparent network devices to prevent them from reaching the outer connections. Transparent network devices modify network traffic, using error detection data, fragmentation data, or timestamps, so that inner connection network traffic inadvertently received by outer connection devices is rejected or ignored by the outer connection network devices. Transparent network devices may use different sequence windows for inner and outer connection network traffic.

Abstract: An interconnect for surfing circuits is presented. The interconnect includes at least one control signal line, at least one data signal line, and at least one variable capacitor coupled to the at least one control signal line and the at least one data signal line, wherein the capacitance of the variable capacitor is configured to be controlled by a control signal on the control signal line so that a velocity of a data signal transmitted on the at least one data signal line is determined by the value of the capacitance of the variable capacitor.

Abstract: One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate a floorplan is substantially reduced because the system generates the floorplan using the reduced netlist instead of using the non-reduced netlist.

Abstract: Some embodiments of the present invention provide a system that performs a print job. During operation, the system receives an email requesting the print job and determines, from the email, a printer associated with the print job. Next, the system configures the print job based on the email. Finally, the system sends the print job to the printer, wherein the print job is executed using the printer.

Abstract: Some embodiments of the present invention provide a system that controls the temperature of a computer system. First, a performance parameter of the computer system is monitored. Next, a future temperature of the computer system is predicted based on the performance parameter. Then, exhaust air from the computer system is mixed with ambient air from outside the computer system based on the predicted future temperature, and the mixed exhaust air and ambient air are channeled through the computer system to control the temperature of the computer system.

Abstract: Some embodiments provide a system for generating a memory-efficient representation of a sequence of electrically connected routing shapes. The memory-efficient representation represents the sequence of electrically connected routing shapes using a sequence of points, such that two consecutive points represent a routing shape. At least some of the points can be represented using a compact representation, thereby reducing the memory required for storing the sequence of points. A full representation specifies a point's location using the point's two-dimensional coordinates, and a compact representation specifies a point's location using one of the point's two-dimensional coordinates and an orientation indicator which indicates the routing shape's orientation. The missing coordinate in a compact representation can be determined from the preceding points. The system can represent a via that joins two routing shapes by assigning different metal layers to the points associated with the two routing shapes.

Abstract: Transparent network devices intercept messages from non-transparent network devices that establish a connection. Transparent network devices modify these messages to establish an inner connection with each other. The transparent network devices mimic at least some of the outer connection messages to establish their inner connection. The mimicked messages and any optional reset messages are intercepted by the transparent network devices to prevent them from reaching the outer connections. Transparent network devices modify network traffic, using error detection data, fragmentation data, or timestamps, so that inner connection network traffic inadvertently received by outer connection devices is rejected or ignored by the outer connection network devices. Transparent network devices may use different sequence windows for inner and outer connection network traffic.

Abstract: One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount.

Abstract: Some embodiments of the present invention provide a system that measures a power efficiency of a computer system. During operation, the system collects telemetry data from a set of sensors within the computer system. Next, the system determines a power consumption of the computer system from the telemetry data and determines a number of input/output operations per second (IOPS) for the computer system from the telemetry data. Finally, the system computes an IOPS per watt metric from the power consumption and the number of IOPS.

Abstract: Described is a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating one or more stop indicators based on actual dependencies, where a given stop indicator indicates the position of a given actual dependency that can lead to different results when the data elements are processed in parallel than when the data elements are processed sequentially, and where the given actual dependency occurs when the pair of conditions matches one or more criteria. Then, the processor executes the instructions for generating the one or more stop indicators.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Abstract: This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process.

Abstract: One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.

Abstract: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Abstract: One embodiment of the present invention provides a system for troubleshooting a computer system. During operation, the system receives an identifier for a suspect computer system, which is suspected of operating abnormally. The system also receives an identifier for a normal computer system, which is operating normally. Next, the system automatically sends a command to be executed to both the suspect computer system and to the normal computer system. The system subsequently receives a response to the command from both the suspect computer system and the normal computer system and compares the responses to determine differences in behavior between the suspect computer system and the normal computer system.

Abstract: A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.

Abstract: One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode.