Abstract: Embodiments of a circuit are described. In this circuit, a receiver includes at least one input node that receives one or more signals from one or more antenna elements. Note that a given signal from a given antenna element may have an associated fixed bandwidth and/or may include directional information corresponding to a region in a space. Moreover, the receiver includes a measurement circuit, coupled to at least the one input node, that determines whether a metric of the given signal exceeds a corresponding threshold. Additionally, control logic in the circuit, which is coupled to the measurement circuit, instructs a communication circuit in the circuit to exit a first power-consumption mode if the metric of at least one of the signals exceeds the corresponding threshold.

Abstract: Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is stored in at least one buffer, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions, by speculatively moving the packets forward even while DMA engines perform their processing to facilitate their transfer.

Abstract: Some embodiments of the present invention provide a system that characterizes the performance of a disk drive at frequencies in a set of frequencies in a frequency range. First, the disk drive is vibrated at each frequency in the set of frequencies, one frequency at a time. During this process, a disk drive performance metric is monitored. Next, the performance of the disk drive is characterized by determining the parameter related to acceleration due to the vibrations for each frequency at which a disk drive performance metric degrades by a predetermined amount from a baseline.

Abstract: Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.

Abstract: One embodiment of the present invention provides a system for determining a list of providers of a commodity. During operation, the system receives a description of the commodity from a customer at a server. Then, the system uses the description to identify a list of providers of the commodity. Next, the system receives a specification of a set of desired provider-traits from the customer. The system then filters the list of providers of the commodity based on the desired provider-traits to obtain a filtered list of providers of the commodity. Finally, the system presents the filtered list of providers to the customer.

Abstract: Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.

Abstract: One embodiment of the present invention provides a system for creating a custom workflow which facilitates performing repetitive processes by aggregating application-screens. During operation, the system receives a request from a client to open an application-screen for an application. In response to the request, the system opens the application-screen. Next, the system receives a request to add the application-screen to a custom workflow. In response to the request, the system adds the application-screen to the custom workflow.

Abstract: The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes.

Abstract: A multi-chip module (MCM) is described. This MCM includes multiple sites, where a given site in the multiple sites includes multiple chips with proximity connectors that communicate information through proximity communication within the MCM via multiple components associated with the given site. Note that the MCM includes global redundancy and local redundancy at the given site. In particular, the global redundancy involves providing one or more redundant sites in the multiple sites. Furthermore, the local redundancy involves providing one or more redundant chips in the multiple chips and one or more redundant components in the multiple components.

Abstract: The described embodiments provide a system that executes program code. While executing program code, the processor encounters at least one vector instruction and at least one vector-control instruction. The vector instruction includes a set of elements, wherein each element is used to perform an operation for a corresponding iteration of a loop in the program code. The vector-control instruction identifies elements in the vector instruction that may be operated on in parallel without causing an error due to a runtime data dependency between the iterations of the loop. The processor then executes the loop by repeatedly executing the vector-control instruction to identify a next group of elements that can be operated on in the vector instruction and selectively executing the vector instruction to perform the operation for the next group of elements in the vector instruction, until the operation has been performed for all elements of the vector instruction.

Abstract: Embodiments of a circuit are described. In this circuit, a transmit circuit provides signals to antenna elements during an acquisition mode, where a given signal to a given antenna element includes at least two frequency components having associated phases, and where the phase of a given frequency component in the given signal is different from phases of the given frequency component for the other antenna elements. Moreover, an output node couples the transmit circuit to the antenna elements that transmit the signals. Note that these signals establish an angle of a communication path between the circuit and another circuit.

Abstract: A method and apparatus for compressing data automatically selects either direct compression of sub-blocks or of compression of transformed sub-blocks to achieve fast and effective data compression. A method and apparatus for decompression automatically performs either direct decompression or decompression and transform operations for respective sub-blocks.

Abstract: One embodiment provides a system that facilitates forwarding a packet. During operation, the system receives a packet with a hierarchically structured variable-length identifier (HSVLI). The system then performs a lookup at a forwarding engine based at least on the packets HSVLI. The system further makes a forwarding decision based on the lookup.

Abstract: An optical device that includes multiple optical modulators having actual operating wavelengths at a given temperature is described. Because of differences between the actual operating wavelengths and target operating wavelengths of the optical modulators, heating elements may be used to thermally tune the optical modulators so that the actual operating wavelengths match corresponding carrier wavelengths in a set of optical signals. Furthermore, control logic in the optical device may assign the optical modulators to the corresponding carrier wavelengths based at least on differences between the carrier wavelengths and the actual operating wavelengths, thereby reducing an average thermal tuning energy associated with the heating elements.

Abstract: A computer system that communicates cryptographic resource utilization information while processing data packets is described. During operation, the system receives a first data packet and generates a second data packet by performing a cryptographic transformation on the first data packet. Next, the system appends auxiliary information to the second data packet. This auxiliary information includes information associated with cryptographic resource utilization during the cryptographic transformation. Then, the system provides the second data packet including the auxiliary information.

Abstract: Some embodiments of the present invention provide a system that generates a load for a computer system in accordance with a predetermined load profile. During operation, the load for the computer system is generated by modulating the load using pulse-width modulation, wherein the load is periodically cycled between at least two different test load levels so that a moving window average of the modulated load follows the predetermined load profile.

Abstract: Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.

Abstract: A look up engine 200 comprising a storage means 212a, 212b for storing a plurality of entries, each entry comprising a value and an associated key value, such that, in operation, a look up is carried out by outputing a value which is associated with the stored key value which matches an input key value. The look up engine 200 comprises a plurality of look up state machines 206a, 206b, 206c, 206d connected in parallel to enable multiple look ups to be carried out concurrently. Each entry comprises an associated skip value, if the skipped bits of the input key value and the associated skip value mismatches, an error message is output to indicate lookup failure. The entries may be stored in a trie format which is constructed by identifying overlapping ranges between the plurality of entries; splitting the identified overlapping ranges; storing the plurality of entries within a trie structure.

Abstract: One embodiment of the present invention provides a system for accessing an encrypted file through a file system. During operation, the system receives a request to access the encrypted file. In response to the request, the system sends an encrypted file key for the encrypted file from the file system to a tamper-resistant module. Next, the tamper-resistant module uses a master secret to decrypt the encrypted file key to restore the file key, wherein the master secret is obtained from an external source by the tamper-resistant module. The system then uses the file key to access the encrypted file.

Abstract: A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.