Abstract: A wafer cooling apparatus characterized by a chamber, a pedestal disposed within the chamber and a mechanism for lowering a semiconductor wafer onto an upper surface of the pedestal. The upper surface of the pedestal is grooved to allow gas trapped between the wafer and the pedestal surface to escape around the periphery of the wafer, thereby minimizing the tendency of the wafer to "skate" across the surface of the pedestal on a thin layer of gas. The method involves extending a number of pins through a grooved cooling surface of the pedestal to contact a wafer, and retracting the pins into the pedestal to lower the wafer to the cooling surface and to force gas trapped between the wafer and the pedestal into the grooves of the pedestal.

Abstract: A suspension system for hanging a susceptor inside a reactor for processing semiconductor wafers. A hanger is provided with a flange at its lower end for supporting the susceptor. A collar has an internal flange which engages with another flange at the upper end of the hanger. The collar flange and the hanger flange each have a trucated, conical contact surface which are in substanitally continuous contact with each other. The mating flanges permit the susceptor to self-center and provide for different rates of thermal expansion of the collar and hanger.

Abstract: A plasma discharge endpoint detection system and method characterized by a plurality of individual data channels which are combined to create a composite function representative of the conditions within a plasma etch chamber. Preferably, a number of the channels are representative of spectral components within the optical spectrum caused by the plasma discharge within the etch chamber. A multi-channel sensor assembly is provided for this purpose including a number of light-guides for guiding light from the plasma discharge to filters and photosensors associated with the multiple channels. Other channels can detect various conditions such as the D.C. bias on a cathode within the plasma etch chamber. The various channels are digitized, weighted and summed within a digital computer to create the composite function from which endpoint and other conditions within the chamber can be determined.

Abstract: A method for endpoint detection in a semiconductor wafer etching system characterized by the steps of: 1) scanning a semiconductor wafer with a narrowly focused laser beam; 2) analyzing a reflected portion of the beam to determine a preferred parking spot on a preferred flat area of the wafer; 3) parking the beam at the preferred spot; and 4) analyzing the reflected portion of the beam to determine when the preferred flat area has been etched through. The beam spot of the laser beam is smaller than the width of the preferred flat area to eliminate noise generated at the transition boundaries of the flat area. Preferably, the wafer is scanned several times along the same beam path to permit the comparison of several scans to determine the preferred parking spot.

Abstract: A method for focussing a radiant energy beam characterized by the steps of scanning a beam of radiant energy across a test pattern including areas of differing reflectivity, detecting the variance in a reflected portion of the scanned beam and adjusting the beam to minimize the variance. Preferably, the test pattern includes areas of varying widths, e.g. relatively non-reflective areas of varying widths separated by reflective areas of uniform widths. As the beam is scanned perpendicularly across the test pattern it will be highly reflected by the reflective areas and will be partially absorbed by the non-reflective areas. If the beam is wider than a non-reflective area a portion of the beam will be absorbed and a portion of the beam will be reflected, resulting in a greater total reflection than if the beam is narrower than the non-reflective region.

Abstract: A matching network matches an output impedance of a source with an input impedance of a load. The matching network includes a plurality of transmission line stubs. Each transmission line stub includes a first transmission line conductor, a second transmission line conductor running parallel to but not in electrical contact with the first transmission line conductor, and ferrite dielectric material between the first transmission line conductor and the second transmission line conductor. A magnetic field is used to vary the relative permeability of the ferrite dielectric material.

Abstract: A method for detecting particles in an ion implantation characterized by the steps of placing a particle sensor within the vacuum chamber of the ion implantation machine, exposing the substrate to an ion beam, thereby dislodging a stream of free particles, and detecting a portion of the free particle sensor. The particle sensor is preferably shielded from radiation to prevent false readings, and is positioned substantially along the plane of rotation of a substrate support wheel. By positioning the particle counter both along the plane of rotation and tangential to the rotation of the wheel at the point of ion impact, the particle counter intercepts the particle stream at the point of maximum particle flux. The apparatus includes a laser beam, a photodetector responsive to a portion of the laser beam scattered off of particles in the particle stream and a lead shield to shield the photodetector from x-rays generated within the vacuum chamber of the ion implantation machine.

Abstract: An improved RIE process is disclosed for etching one or more openings in a layer of an oxide of silicon on a semiconductor wafer characterized by a contact angle of at least 80.degree., with respect to the plane of the oxide layer, and highly selective to silicon which comprises flowing an inert gas and CHF.sub.3 into an RIE chamber while maintaining respective gas flows within a range of from about 15 to about 185 sccm of inert gas and from about 15 to about 60 sccm of CHF.sub.3, with a total gas flow not exceeding about 200 sccm, and a ratio of inert gas to CHF.sub.3 ranging from about 1:1 to about 10:1. A plasma is maintained in the RIE chamber during the gas flow at a power level within a range of from about 400 to about 1000 watts. In a preferred embodiment, CF.sub.4 gas is also flowed into the RIE chamber within a range of from about 1 to about 10 sccm to control the selectivity of the etch to silicon, and the wafer is immersed in a magnetic field of 1 to 120 gauss during the etching process.

Abstract: The present invention improves the interaction of a virtual memory systems and a garbage collection system, thereby reducing garbage collection effort and improving virtual memory performance. The method includes the steps of: (1) developing a secondary memory (e.g. disk) dirty page map; (2) developing a saved state map from a primary memory (e.g. RAM) dirty page map; (3) using the secondary memory dirty page map and the primary memory dirty page map to effectively reduce the size of the base set; (4) performing a garbage collection routine on at least a segment of the heap based upon the effectively reduced base set; and (5) performing a virtual memory routine using the primary memory dirty page map and the saved state map. The apparatus of the present invention implements the method on a digital computer system with a combination of hardware and software.

Abstract: An improved method is disclosed for forming one or more N- LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises the steps of: forming a polysilicon gate electrode over a semiconductor wafer substrate, N- doping the substrate to form one or more N- LDD regions, selectively depositing polysilicon on the polysilicon sidewalls of the gate electrode, and then N+ doping the substrate to form N+ source and drain regions in the substrate using the selectively deposited polysilicon as a mask over the N- LDD regions previously formed in the substrate.

Abstract: A process is disclosed for the treatment of the backside or back surface of a semiconductor wafer such as a silicon wafer. By spacing the back side of a semiconductor wafer a predetermined distance from a cathode in a vacuum chamber and controlling the rf power and the pressure, a confined plasma may be used both to clean the back side of the wafer to remove impurities, including moisture and other occluded gases; as well as to deposit a layer of oxide on the back surface of the wafer to inhibit subsequent deposition of poorly adherent materials on the back side of the wafer which might otherwise flake off during processing of the front side of the wafer to form integrated circuits thereon.

Abstract: An improved planarization process is disclosed which comprises depositing over a patterned integrated circuit structure on a semiconductor wafer a conformal insulation layer by ECR plasma deposition of an insulation material. The ECR plasma deposition is carried out until the trenches or low regions between adjacent raised portions of the structure are completely filled with insulation material. A planarization layer of a low melting glass material, such as a boron oxide glass, is then flowed as it is deposited over the integrated circuit structure to a depth or thickness sufficient to cover the highest portions of the ECR plasma deposited insulation layer. This planarization layer is then anistropically etched back sufficiently to provide a planarized surface on the ECR plasma deposited insulation layer.

Abstract: A method for endpoint detection in a semiconductor wafer etching system characterized by the steps of: (1) scanning a semiconductor wafer with a narrowly focussed laser beam; (2) analyzing a reflected portion of the beam to determine a preferred parking spot on a preferred flat area of the wafer; (3) parking the beam at the preferred spot; and (4) analyzing the reflected portion of the beam to determine when the preferred flat area has been etched through. The beam spot of the laser beam is smaller than the width of the preferred flat area to eliminate noise generated at the transition boundaries of the flat area. Preferably, the wafer is scanned several times along the same beam path to permit the comparison of several scans to determine the preferred parking spot.

Abstract: A matching network matches an output impedance of a generator with an input impedance of a load. The matching network includes a first variable impedance element, a second variable impedance element, a reflected power detector and a control circuit. Each of the first variable impedance elements are constructed using magnetically saturable reactors. For example, each magnetically saturable reactor may be a transformer composed of primary and secondary windings wound around a non-linear ferromagnetic core. The reflected power detector detects power reflected from the matching network to the generator. The control circuit receives from the reflected power detector a signal which represents the changes in reflected power. Using this feedback the control means varies the impedance through the first variable impedance element and the second variable impedance element until the reflected power is negligible.

Abstract: A process is disclosed for the etching of a tungsten layer on a semiconductor wafer through a photoresist mask to form a pattern of tungsten lines on the wafer. The process is characterized by a high selectivity to photoresist material and resistance to lateral etching or undercutting of the tungsten beneath the photoresist mask resulting in good profile control, i.e., low critical dimension loss in the etched tungsten pattern. The process comprises flowing SF.sub.6, N.sub.2, Cl.sub.2 gases into an etch chamber while maintaining a plasma in the chamber. In a preferred embodiment, the wafer in the etch chamber is immersed in a magnetic field during the etch to further enhance the selectivity of the etch to photoresist.

Abstract: A method for preventing cross-contamination of semiconductor wafers during processing comprising covering a surface portion of a support assembly with a process compatible material, engaging a semiconductor wafer with the support assembly, processing the wafer while it is engaged with the support member, and removing the process compatible material from the support assembly after said material is considered to be contaminated. A shield particularly adapted for this process includes a shield portion made from a process compatible material and a process-compatible adhesive for attaching the shield portion to the support assembly.

Abstract: An epitaxial reactor system provides for enhanced gas flow control and, thus, deposition uniformity. Gross reactant gas flow is set by a main flow controller which delivers unequal amounts to a reaction chamber via two nozzle assemblies. A supplemental flow controlled by an auxiliary flow controller is used to balance the flow rates through the nozzle assemblies so as to reduce spiralling of the gas flow within the chamber. Vertical ridges on a shroud within the reaction chamber help guide incoming gases vertically, further minimizing spiralling. The direction of gas flow from each nozzle assembly is controlled by two actuators, one controlling orientation along a coarse diagonal to obtain an overall vertical uniformity of deposition; the other actuator controls orientation along a fine diagonal to balance inter- and intra-wafer deposition uniformity. This arrangement optimizes the convenience in attaining vertical uniformity.

Abstract: A thermal reactor system for semiconductor processing incorporates a reaction vessel with a rectangular quartz tube with reinforcing parallel quartz gussets. The gussets enable sub-ambient pressure processing, while the rectangular tube maximizes reactant gas flow uniformity over a wafer being processed. The gussets facilitate effective cooling, while minimally impairing heating of the wafer by allowing minimal wall thickness. The thermal reactor system further includes a gas source for supplying reactant gas and an exhaust handling system for removing spent gases from and establishing a reduced pressure within the reaction vessel. An array of infrared lamps is used to radiate energy through the quartz tube; the lamps are arranged in a staggered relation relative to the quartz gussets to minimize shadowing. In addition, other non-cylindrical gusseted vessel geometries are disclosed which provide for improved sub-ambient pressure thermal processing of semiconductor wafers.

Abstract: A sample-and-hold circuit distinguished by its lack of a storage capacitor. The circuit includes a delay line and a signal following circuit coupled to the delay line which is synchronized with the delay line's propagation rate. In several embodiments of the invention a multi-tap delay line is used, and the signal following circuits variously include an electronic switch or linear interpolation circuits. In several other embodiments of this invention a gate of a FET is used as the delay line, and the signal following circuits include the drain and source of the FET. By substituting a delay line and signal following means for a storage capacitor, extremely fast sample-and-hold circuits may be obtained.

Abstract: An interconnect structure for electrically coupling conductive paths on two adjacent, rigid substrates, such as PC boards or IC chips. The interconnect structure includes a number of buttons formed on a first substrate, and a number of contacts formed on a second substrate. The buttons are elastically deformable, and include a resilient core made from an organic material such as polyimide, and a metallic coating formed over the core. The two substrates are compressed between mounting plates such that the buttons are pressed against the contracts to make electrical contact.