Patents Represented by Attorney, Agent or Law Firm Peter J. Meza. Esq.
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Patent number: 6777287Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.Type: GrantFiled: May 23, 2003Date of Patent: August 17, 2004Assignee: Fujitsu LimitedInventors: Soichiro Ozawa, Shan Sun, Hideyuki Noshiro, George Hickert, Katsuyoshi Matsuura, Fan Chu, Takeyasu Saito
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Patent number: 6560137Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.Type: GrantFiled: January 16, 2001Date of Patent: May 6, 2003Assignee: Ramtron International CorporationInventors: Judith E. Allen, Lark E. Lehman, Dennis R. Wilson
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Patent number: 6535446Abstract: A low voltage boost circuit suitable for use in a ferroelectric memory is realized implementing five N-channel devices and two ferroelectric capacitors. The voltage on a word line is boosted using charge sharing techniques in order to assure proper operation at lower power supply voltage conditions. In operation, the gate of an N-channel pass gate is boosted to supply a full VDD voltage on the bottom electrode of a ferroelectric capacitor, which capacitively couples into the word line for an efficient word line voltage boost.Type: GrantFiled: May 24, 2001Date of Patent: March 18, 2003Assignee: Ramtron International CorporationInventor: Gary Moscaluk
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Patent number: 6501698Abstract: A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, data can be transferred (1) from the DRAM array to the read data transfer areas, (2) from the write data transfer areas to the DRAM array, and (3) from the write data transfer areas to the read data transfer areas.Type: GrantFiled: November 1, 2000Date of Patent: December 31, 2002Assignee: Enhanced Memory Systems, Inc.Inventor: Kenneth J. Mobley
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Patent number: 6459609Abstract: An implementation of 1T/1C nonvolatile ferroelectric RAMS without using any reference cells—the polarization state in a memory cell is determined by applying two consecutive plate pulses on the ferroelectric capacitor in the memory cell, preamplifying the bit line voltages corresponding to these two plate pulses, and comparing the preamplified voltages. The two consecutive plate pulses have the same polarity.Type: GrantFiled: December 13, 2001Date of Patent: October 1, 2002Assignee: Ramtron International CorporationInventor: Xiao Hong Du
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Patent number: 6445608Abstract: A FRAM configurable output driver circuit allows the user to configure the output driver for either CMOS level push/pull operation or true open drain operation. This configuration is stored in a non-volatile memory including a FRAM cell and a standard logic latch. The configuration data is restored to the latch on powerup. The user is able to change the configuration at any time. Any changes to the configuration are stored in the non-volatile memory.Type: GrantFiled: September 10, 2001Date of Patent: September 3, 2002Assignee: Ramtron International CorporationInventors: Kurt Schwartz, Michael Alwais
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Patent number: 6430093Abstract: A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.Type: GrantFiled: May 24, 2001Date of Patent: August 6, 2002Assignee: Ramtron International CorporationInventors: Jarrod Eliason, William F. Kraus
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Patent number: 6423592Abstract: A method of patterning and etching an integrated circuit ferroelectric capacitor uses a layer of PZT which has the same composition as the capacitor PZT as a temporary encapsulation during PZT grain growth annealing. The temporary encapsulation PZT also serves as a hard mask to pattern the top electrode and the capacitor PZT layers for a capacitor-on-oxide structure, i.e., two-layer-one-step patterning. The process of the present invention can also be modified as a three-layer-one-step patterning process and can be applied to a capacitor-on-plug structure.Type: GrantFiled: June 26, 2001Date of Patent: July 23, 2002Assignee: Ramtron International CorporationInventor: Shan Sun
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Patent number: 6362675Abstract: An octal transparent latch or D-type register (or flip-flop) integrated circuit device may be packaged in an industry standard logic pin-out and configuration but having nonvolatile properties such as automatically recording the output state in nonvolatile form and restoring it on power up. The nonvolatile memory elements are ideally ferroelectric capacitors, using well known ferroelectric materials such as PZT, SBT, or BST or other ferroelectric materials. EEPROM, Flash, SNOS, or other writeable nonvolatile technologies can also be used. In a particular embodiment disclosed herein, the nonvolatile elements of the integrated circuit device are written only when the latched state changes to reduce write endurance changes thereto and data changes on either the input or output data lines that are not latched have no effect.Type: GrantFiled: July 11, 2000Date of Patent: March 26, 2002Assignee: Ramtron International CorporationInventor: Michael Alwais
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Patent number: 6358755Abstract: A ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and third dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a second viaType: GrantFiled: August 17, 2000Date of Patent: March 19, 2002Assignee: Ramtron International CorporationInventor: Thomas A. Evans
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Patent number: 6330636Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device incorporating a static random access memory (“SRAM”) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page “hit” latency, faster page “miss” latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read “hit”.Type: GrantFiled: January 29, 1999Date of Patent: December 11, 2001Assignee: Enhanced Memory Systems, Inc.Inventors: David W. Bondurant, Michael Peters, Kenneth J. Mobley
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Patent number: 6287637Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.Type: GrantFiled: October 27, 1999Date of Patent: September 11, 2001Assignee: Ramtron International CorporationInventors: Fan Chu, Glen Fox, Brian Eastep
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Patent number: 6275425Abstract: A boost circuit for a ferroelectric memory operated in a low voltage supply environment is achieved by floating a local supply voltage and using a single boost via one or more appropriately sized ferroelectric boost capacitors to elevate the local supply level to the desired boosted voltage. When boosting is not required, the local supply voltage is tied to the system external power supply through an appropriately sized PMOS transistor.Type: GrantFiled: November 16, 2000Date of Patent: August 14, 2001Assignee: Ramtron International CorporationInventor: Jarrod Eliason
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Patent number: 6252793Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.Type: GrantFiled: September 15, 2000Date of Patent: June 26, 2001Assignee: Ramtron International CorporationInventors: Judith E. Allen, William F. Kraus, Lark E. Lehman, Dennis R. Wilson
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Patent number: 6242299Abstract: A continuous barrier layer is formed after a local interconnect metal layer is formed between the top electrode of a ferroelectric capacitor and the source/drain contact of a memory cell transistor in an integrated ferroelectric memory. After contact has been made to the top electrode of the ferroelectric capacitor, a thin dielectric layer is deposited using a material that provides an effective hydrogen barrier to the ferroelectric capacitor. The barrier layer minimizes damage to the ferroelectric capacitor and thus improves electrical performance.Type: GrantFiled: April 1, 1999Date of Patent: June 5, 2001Assignee: Ramtron International CorporationInventor: George Hickert
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Patent number: 6238933Abstract: Ferroelectric switching properties are severely degraded in a hydrogen ambient atmosphere. By controlling the polarity of the capacitors in a ferroelectric memory during the manufacturing process, the amount of degradation can be significantly reduced. After metalization of a ferroelectric memory wafer, all of the ferroelectric capacitors are poled in the same direction. The polarization vector is in a direction that helps to counteract hydrogen damage. A hydrogen gas anneal is subsequently performed to control underlying CMOS structures while maintaining ferroelectric electrical properties. The wafer is then passivated and tested.Type: GrantFiled: May 6, 1999Date of Patent: May 29, 2001Assignee: Ramtron International CorporationInventors: Shan Sun, Steven D. Traynor
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Patent number: 6232153Abstract: A plastic package assembly method suitable for ferroelectric-based integrated circuits includes a strict thermal budget that reduces the time at temperature for four key processing steps: die attach cures, die coat cures, molding cures, and marking cures. The plastic package assembly method uses low temperature mold and die coat materials, as well as low temperature curable inks or laser marking in order to minimize degradation of electrical performance, thus improving yields and reliability. The assembly method uses a snap cure die attach step, a die coat followed by a room temperature cure, and formation of the plastic package with room temperature curable molding compounds not requiring a post mold cure. Front and back marking of the plastic package is accomplished using either an infrared or ultraviolet curable ink followed by minimum cure time at elevated temperature, or by using laser marking.Type: GrantFiled: June 4, 1998Date of Patent: May 15, 2001Assignee: Ramtron International CorporationInventors: Sanjay Mitra, Vic Lau
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Patent number: 6211542Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.Type: GrantFiled: May 27, 1998Date of Patent: April 3, 2001Assignee: Ramtron International CorporationInventors: Brian Lee Eastep, Thomas A. Evans
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Patent number: 6203608Abstract: The ferroelectric thin film is formed from a liquid composition by the sol-gel processing which has a large amount of polarization, remarkably improved retention and imprint characteristics as compared with a PZT, minute grains and fine film quality, homogeneous electrical properties, and low leakage currents and which is suited for nonvolatile memories. The ferroelectric thin film of the present invention comprising a metal oxide represented by the general formula: (Pbv Caw SrX LaY)(ZrZ Ti1−Z)O3, wherein 0.9≦V≦1.3, 0≦W≦0.1, 0≦X≦0.1, 0<Y≦0.1, 0<Z≦0.Type: GrantFiled: April 15, 1998Date of Patent: March 20, 2001Assignees: Ramtron International Corporation, Mitsubishi Materials CorporationInventors: Shan Sun, Thomas Domokos Hadnagy, Tom E. Davenport, Hiroto Uchida, Tsutomu Atsuki, Gakuji Uozumi, Kensuke Kegeyama, Katsumi Ogi
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Patent number: 6201726Abstract: A ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and third dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a second viaType: GrantFiled: June 5, 2000Date of Patent: March 13, 2001Assignee: Ramtron International CorporationInventor: Thomas A. Evans