Abstract: A ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and third dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a second via

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, an a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance. The encapsulation technique can also be used to improve the performance of ferroelectric transistors and other devices.

Abstract: A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.

Abstract: An RC equivalent delay circuit includes an input node, an output node, a feedback node, and an intermediate node; a first inverter having an input coupled to the input node and an output coupled to the intermediate node; a second inverter having an input coupled to the intermediate node and an output coupled to the feedback node; a third inverter having an input coupled to the feedback node and an output coupled to the output node; and one or two switches having a first input coupled to the input node, a second input coupled to the feedback node, and an output coupled to the intermediate node.

Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.

Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.

Abstract: A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.

Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance. The encapsulation technique can also be used to improve the performance of ferroelectric transistors and other devices.

Abstract: A method of driving a sense amplifier having at least one input/output node and at least one latch node the method includes the steps of initially setting the latch node to a first logic state such that the sense amplifier is disabled, adjusting the latch node voltage in one or more discrete levels, and finally setting the latch node to a second logic state such that the sense amplifier is enabled.

Abstract: A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

Abstract: An iridium oxide local interconnect method for a ferroelectric memory cell includes the steps of forming a conductive layer that extends from a source/drain contact of the transistor proximate to an electrode contact of the ferroelectric capacitor and forming an iridium oxide local interconnect extending from the source/drain contact of the transistor to the electrode contact of the ferroelectric capacitor. The conductive layer is laterally terminated not less than one-half micron from the electrode contact of the ferroelectric capacitor. The conductive layer can include an upper iridium layer and a bottom titanium nitride layer, or can include a single layer of completely reacted titanium nitride. After the local interconnect is formed a top oxide layer is deposited. A late recovery anneal is then performed in oxygen at an elevated temperature to rejuvenate the electrical characteristics of the ferroelectric capacitor. Finally, a bit line contact is opened and metalized.

Abstract: A method of driving a selected plate line segment in a 1T/1C memory, the method including the steps of logically combining an odd word line signal and an even word line signal to form a first logic signal, logically combining the first logic signal with a plate clock signal to form a second logic signal, latching the second logic signal, and driving the selected plate line segment with the latched second logic signal.

Abstract: A sense amplifier cell layout for use in a 1T/1C ferroelectric memory array includes a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal and a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal, wherein the combined width of the first and second sense amplifiers is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

Abstract: A dual-level metalization method for ferroelectric integrated circuits includes the steps forming a planarized oxide layer over a partially formed integrated circuit ferroelectric device, forming a cap layer over the planarized oxide layer, forming vias into the planarized oxide layer and cap layer to provide access to the desired first-level metal contacts, and metalizing the selected first-level metal contacts with second-level metal. The cap layer can be doped or undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, or manganates such as doped and undoped PZT (lead zirconate titanate), BST (barium strontium titanate), or SBT (strontium bismuth tantalate).

Abstract: A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.

Abstract: A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider.

Abstract: A voltage boost circuit allows a reference input voltage to be boosted in a manner that is less sensitive to variations in power supply voltage levels, temperature, and semiconductor process used. A nominal boost voltage of approximately 1.5 volts is supplied, even at very low power supply voltages. A boost voltage less than 1.5 volts is supplied down to power supply voltages of approximately 1.8 volts.

Abstract: A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider.