Abstract: A metastable sense circuit includes an input latch and a sense latch. The input latch passes data from the input to the output in a transparent mode and retains data at the output in a hold mode in response to a clock signal. The output of the input latch is coupled to an input of the sense latch. A logic signal is provided at the output of the sense latch responsive to an occurrence of a metastable state of the input latch in a transparent mode and retains data at the output in a hold mode in response to a clock signal. The input section of the sense latch includes a reference voltage generator that tracks changes in the logic switching threshold of the output of the input latch.

Abstract: A logarithmic amplifier includes a first diode wherein the anode receives an input signal input signal current and a standing current. The cathode of the first diode is coupled to the emitter of a PNP transistor. The collector of the PNP transistor is coupled to the anode of a second diode. A bias current is added to the emitter and substracted from the collector of the PNP transistor to provide a lower emitter impedance. The cathode of the second diode is coupled to a negative supply voltage through a load resistor. A feedback network including an emitter coupled pair of NPN transistors samples the voltage at the anode of the second diode and sinks a current from the base of the PNP transistor. The voltage at the anode of the first diode is amplified to provide a logarithmic output voltage. The output voltage may be attenuated and applied to the base of the PNP transistor.

Abstract: An optical receiver circuit for an incoming optical signal having a variable power level includes an optical detector for receiving the optical signal and generating a current therefrom which varies with the optical signal power level. The current so generated is applied to a transimpedance amplifier. An automatic gain control (AGC) drive circuit is connected around the amplifier thereby increasing its dynamic range. The AGC drive circuit drives a FET which has one side thereof connected to the transimpedance amplifier for shunting current from the input thereof. A negative feedback circuit comprising an amplifier is connected across the FET, which comprises the resistive feedback element, thus reducing the FET resistance by a factor of 1+T, where T is the feedback circuit loop gain.

Abstract: A high-impedance FET circuit in which the anode of a diode is electrically connected to the first side of the FET and the diode's cathode is connected to the FET gate. The diode biases the FET to reduce second side current when the second side is at a positive potential relative to the diode cathode. Such circuits placed back-to-back accommodate signals of both polarities and are used as a high impedance element in a low-pass filter implemented in an integrated circuit. An equivalent symmetrical circuit implemented with two enhancement FETs is also disclosed.

Abstract: A binarily weighted FET attenuator implemented in integrated form. The resistance of the vertical branches to the horizontal branches is at a ratio of 2:1. Each vertical branch includes a FET switch for switching between ground and a summing amplifier and each horizontal branch includes a FET permanently biased to conduct. Thus, variations in the value of r.sub.on, the resistance of each FET when conducting, due to fabrication process and temperature are compensated for due to the presence of FETs in both the vertical and horizontal legs of the attenuator.

Abstract: An electro-optical transducer module comprises a substrate having a planar main surface, an electro-optical transducer adhered directly to the main surface of the substrate, and an optical fiber adhered directly to the main surface of the substrate. The optical fiber has an end face in optically coupled relationship with the transducer. A handling element is adhered to the fiber, the fiber being between the handling element and the main surface of the substrate.

Abstract: A complementary composite PNP transistor includes a p-channel JFET and an operational amplifier coupled to form an ideal PNP transistor. The positive input of the operational amplifier forms the base of the composite transistor and the drain of the JFET forms the collector of the composite transistor. The anode of a diode-connected NPN transistor forms the emitter of the composite transistor, while the cathode is coupled to the source of the JFET. The diode-connected transistor provides complementary current-voltage characteristics for the composite PNP transistor since the saturation current and g.sub.m of the composite transistor are equal to that of an NPN transistor.

Abstract: A solid-state electrical circuit (10) includes a reference diode (D1) and multiple diodes (D3-D14) connected in electrical series to produce a substantially temperature-invariant output reference voltage. The reference diode is characterized by a forward voltage drop (V.sub.D1) that changes in accordance with a temperature coefficient. The multiple diodes, which have selected junction areas (A1 and A2) and receive one of two different forward-bias currents (I1 and I2), are electrically interconnected to establish a net voltage (.DELTA.V.sub.Di) that equals the forward voltage drop across the reference diode and changes in accordance with a net temperature coefficient of substantially equal magnitude but of opposite sign to the temperature coefficient of the reference diode. The output reference voltage equals the sum of the forward voltage drop across the reference diode and the net voltage established by the multiple diodes.

Abstract: A regenerative comparator with a differential amplifier pair of transistors (Q.sub.1D, Q.sub.1E, Q.sub.2D, and Q.sub.2E) and a differential regenerative pair of transistors (Q.sub.3D, Q.sub.3E, Q.sub.4D, and Q.sub.4E), utilizes one or more of the following three techniques to reduce hysteresis by reducing the amount of charge storage in transistors. First, the transistors are arranged in a bootstrap cascode configuration having a depletion mode device (Q.sub.D) and an enhancement mode device (Q.sub.E). Second, a differential amplifier pair source-coupling implementation (D.sub.1 -D.sub.4, Q.sub.5A -Q.sub.5C, and Q.sub.6A -Q.sub.6C) allows current to flow through the transistors of the differential amplifier pair and differential regenerative pair independent of whether current is flowing through the branch (52 or 4) that connects the emitters or sources of the enhancement devices of the amplifier pair and regenerative pair. Third, the comparator includes keep-alive current sources (Q.sub.KA1 -Q.sub.

Abstract: A data acquisition system suitable for use in a SAR type A/D converter has a metastable sense feature capable of sensing and resolving a metastable condition in the input latch structure of a SAR in order to enable the acquisition of each bit of a digital output word within no more than two clock cycles. In one embodiment the data acquisition system includes a master latch having an input for receiving a digital input signal and a plurality of input latches wherein the inputs of the input latches are coupled together and to the output of the master latch. A sense latch is further included wherein the input of the sense latch is coupled to the output or sense node in the master latch for sensing a metastable condition with the master latch. A plurality of secondary latches is included wherein the inputs of the secondary latches are coupled together and to the output of the sense latch.

Abstract: A triggering control circuit varies a holdoff period for one sweep cycle whereby to lock triggering to a different, selected event viewable on an oscilloscope.

Abstract: The present invention constitutes a memory system comprising a multiple number of individual memory units (40-47) for storing digital data from a variable number of data input streams and for efficiently using the memory capacities of the memory units in the system by controlling the routing of data between the memory units. Each one of the memory units includes a set of input multiplexers (100-103), a set of shift/shadow registers (110-113) and a memory component (120) having a RAM memory array (121). The components of the memory units are implemented on a single integrated circuit chip. The input multiplexers allow alternate data streams to be selected for input to the shift/shadow registers. The shift/shadow registers are operative for enabling data to be transferred to and from the memory array at speeds slower than the rate at which these data are received by the system.

Abstract: A method for increasing the resolution of measurements taken using a counter-timer is provided that includes the steps of selecting a magnifier value and displaying the selected magnifier value on a CRT screen, performing a trial measurement with the counter-timer set at a fixed gate time and displaying the trial measurement result, calculating a new gate time from the magnifier value and trail measurement results, displaying the new gate time, and performing a second measurement with the counter-timer set to the new gate time and displaying the second measurement result.

Abstract: An inductor and carrier suitable for mounting on a mounting substrate includes an etched sheet of a bonded copper layer and polyimide film to form a film carrier. The periphery of the film carrier is patterned with a plurality of windows and a plurality of conductors, each conductor having a bent-up tab and and end portion terminating at the periphery within the respective window. A microminiature inductor core having a plurality of insulated windings is soldered to the respective bent-up tab of each conductor and the end portion of each conductor is then welded to bonding pads on the mounting substrate.

Abstract: A serial-parallel-serial, charged-coupled device includes an array of horizontal rows and columns of closely spaced charge storage cells. Each storage cell is formed by an electrode covering an insulation layer above a semiconductor substrate. The semiconductor substrate of each storage cell includes a channel region for conducting carriers laterally through the storage cell. The channel region of each storage cell included both in a first row of the array and in any column of the array has a tilted potential gradient providing an electric field facilitating charge carrier drift within the channel region in two lateral directions, toward a neighboring storage cell of the first row and also toward a neighboring storage cell of its column.

Abstract: An apparatus and method for calibrating an interleaved digitizer includes a system oscillator for generating a master clock signal and two or more cascaded phase shifting circuits for producing clock signals that are phase shifted copies of the master clock signal. The calibrator further includes two or more A/D converters for digitizing the master clock signal at time intervals provided by the phase shifted clock signals to produce a digitized output. The digitized output is then stored in a memory. Once stored, the digitized output is compared to predetermined reference levels and the phase shift of the phase shifting circuits is appropriately adjusted as a function of the difference between the stored digitized output and the predetermined reference levels.

Abstract: A sample and hold network is provided having an analog multiplier that multiplies the analog input signal by a sinusoidal strobe signal to produce a multiplied signal. The multiplied signal is filtered by a bandpass differentiating filter and is combined in a differential amplifier with the analog input signal to yield a periodically sampled and held version of the analog input signal. The bandpass differentiating filter attenuates or eliminates undesirable DC and frequency components.

Abstract: An interferometer comprises an optical system for generating an interference pattern of a predetermined configuration in a focal plane of the interferometer, and a detector device for measuring the distribution of optical power over the focal plane. The detector device comprises a body of semiconductor material having first and second opposite main surfaces, one of which surfaces lies substantially in the focal plane of the interferometer. The body of semiconductor material has a region of a first conductivity type and a channel of a second, opposite conductivity type at the first surface thereof and bounded by the region of the first conductivity type. The configuration of the channel conforms substantially to the predetermined configuration of the interference pattern. The semiconductor material responds to electromagnetic radiation in a given spectral region by generating charge carriers. Charge carriers that are created in or diffuse into the channel are confined in the channel.

Abstract: A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge samples, the four sequences being offset in phase relative to each other by 90.degree. within the cycle of a clock signal. At least one of the serial registers comprises a first lead-in gate pair and a second lead-in gate pair over the lead-in section, the second lead-in gate pair being between the first lead-in gate pair and the transfer section. The first lead-in gate pair and the second lead-in gate pair are each driven at the frequency of the clock signal, the drive signal applied to the second lead-in gate pair being retarded in phase relative to that applied to the first lead-in gate pair by 90.degree. within the cycle of the clock signal.

Abstract: A plate-like body (e.g., a silicon wafer) at least about 0.5 mm thick that is to be thinned is reinforced by applying to one main surface, in adhesive relationship thereto, a coating of a finely divided material which is fused to form a hard mechanically supportive coating. The body is thinned from the second main surface to a thickness less than about 250 .mu.m. For a silicon body, the mechanically supportive coating comprises at least about 18% silicon.