Patents Represented by Attorney, Agent or Law Firm Peter K. McLarty
  • Patent number: 7279397
    Abstract: A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate the isolation region (305) to create a threshold voltage compensation region (318). After the compensation region (318) is created, the hard mask layer (304, 308) is patterned (218) to create a patterned hard mask. The patterned hard mask is then used in forming (222) a trench (323) in the isolation region (305) near the compensation region (318), and the trench (323) is then filled (224) with a dielectric material (338).
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: October 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Mehrotra, Amitava Chatterjee
  • Patent number: 7279406
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of transistor devices. A strain profile is selected for the channel regions (104). Recessed regions are formed (106) in active regions of a semiconductor device after formation of gate structures according to the selected strain profile. A recess etch (106) is employed to remove a surface portion of the active regions thereby forming the recess regions. Subsequently, a composition controlled recess structure is formed (108) within the recessed regions according to the selected strain profile. The recess structure is comprised of a strain inducing material, wherein one or more of its components are controlled and/or adjusted during formation (108) to tailor the applied vertical channel strain profile.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: October 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Elisabeth Marley Koontz
  • Patent number: 7276408
    Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: October 2, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Yuanning Chen, Mark Visokay
  • Patent number: 7268073
    Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Deepak A. Ramappa, Mona Eissa, Christopher Lyle Borst, Ting Y. Tsui
  • Patent number: 7268399
    Abstract: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Robert C. Bowen, Yuguo Wang
  • Patent number: 7268045
    Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Philip L. Hower, Taylor R. Efland
  • Patent number: 7268088
    Abstract: One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Hiroaki Niimi
  • Patent number: 7262409
    Abstract: The present invention provides, in one aspect, a method of imaging a microelectronics device 100. The method comprises cleaning, when contaminants are preset, a sample of a microelectronics device 100 to be imaged with a first solution comprising hydrofluoric acid, an inorganic acid and water, exposing the sample to a second solution comprising hydrofluoric acid, an inorganic acid and an organic acid, wherein the second solution forms a contrast between different regions within the sample, and producing an image of the contrasted sample.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: August 28, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Lancy Y. Tsung, Adolfo Anciso, Doug Matheson
  • Patent number: 7262468
    Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: August 28, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
  • Patent number: 7262129
    Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: August 28, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Zhijian Lu, Thomas M. Wolf, Scott W. Jessen
  • Patent number: 7262471
    Abstract: A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: August 28, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Shanjen Pan, Sameer Pendharkar, James R. Todd
  • Patent number: 7256121
    Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: August 14, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Duofeng Yue, Stephan Grunow, Satyavolu S. Papa Rao, Noel M. Russell, Montray Leavy
  • Patent number: 7253072
    Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: James D. Bernstein, Lance S. Robertson, Said Ghneim, Nandu Mahalingam, Benjamin Moser
  • Patent number: 7253043
    Abstract: The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In particular, one more types of dopant materials are implanted in a channel region, an extension region and/or source/drain regions to mitigate the establishment of a conduction path and the accumulation of electrons in the channel region that can result in an unwanted leakage current.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jean-Pierre Colinge, Weize Xiong
  • Patent number: 7253086
    Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Lindsey Hall
  • Patent number: 7250349
    Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: July 31, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Francis G. Celii, Mahesh J. Thakre, Scott R. Summerfelt
  • Patent number: 7250334
    Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.
    Type: Grant
    Filed: July 31, 2004
    Date of Patent: July 31, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Darius L. Crenshaw, Byron L. Williams, Alwin Tsao, Hisashi Shichijo, Satyavolu S. Papa Rao, Kenneth D. Brennan, Steven A. Lytle
  • Patent number: 7250372
    Abstract: A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t* is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: July 31, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: James B. Friedmann, Christopher C. Baum
  • Patent number: 7244654
    Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pr Chidambaram, Douglas T. Grider, Brian A. Smith, Haowen Bu, Lindsey Hall
  • Patent number: 7244642
    Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Steven A. Vitale, Hyesook Hong, Freidoon Mehrad