Abstract: An input signal (IN) and a threshold signal (Vt) are coupled to an output terminal (2) via the base-emitter paths of first (Q1) and second (Q2) transistors having respective collector electrodes connected to a supply voltage source (3). The output terminal (2) is coupled to a source of reference potential (4) via a first resistor (Re) and is coupled via a second resistor (Rd) to a selected plate of a capacitor (C1) that is connected between the collector and base electrodes of the second transistor (Q2). Circuit impedances are scaled such that Re>Rd>R1 wherein Re and Rd are the values of the first and second resistors, respectively, and R1 is a component of the output impedance of the threshold signal source (5).

Abstract: In order to increase the speed of the transfer of control data to an OSD circuit, and to eliminate "holes" in memory caused by the use of memory mapped registers, dual use is made of the serial data port of the OSD circuit to accomplish two distinct tasks, serial transfer of graphics data and serial transfer of the control data. The on-screen display apparatus includes an OSD circuit for generating an graphics signal for display on a display screen, a controller coupled to the OSD circuit, for controlling the OSD circuit, and a VRAM including a first area for storing graphics data and a second area for storing control data for the OSD circuit. The VRAM has a parallel input/output port coupled to the controller and a serial output port coupled to the OSD circuit, the serial output port conveys the graphics data from the first area of the VRAM to the OSD circuit for processing and display.

Abstract: A digital filter (20,30) separates an M-bit (12) chrominance component (C12) from an N-bit (8) digital composite video signal (CV) supplied thereto, M (12) being greater than N (8) due to arithmetic operations (24,44,46,50) required for the separation. The separated M bit chrominance component is reduced to N-bits and subtracted from the composite video signal to provide a separated luminance component. For bit reduction, the separated chrominance component (C12) is subjected to symmetrical rounding (100A or 100B and 104) and limiting (104). Advantageously, symmetrical rounding of the chrominance component provides reduces a tendency for the luminance component to exhibit contouring when displayed.

Abstract: A VCR or laserdisc player includes circuitry for detecting a code provided by VCR tapes, tape cassettes, or laser videodiscs, which indicates that the material recorded on the videotape or videodisc has been recorded in a compressed fashion to enable proper playback on a 16.times.9 television receiver. In response to detection of this code, the VCR or laserdisc player applies a DC signal to the chrominance output terminal of its S-Video connector. Circuitry in the television receiver detects the DC signal on the chrominance terminal of its S-Video input connector, and controls a wide-screen processor to expand the image by displaying it over the entire width of the 16.times.9 display screen.

Abstract: A method of transmitting and decoding biphase coded signals individually representing separate data services and inserted in the line blanking interval of a video signal greatly increases the probability of avoiding the effects of anticoincidence errors. A unique start code is allocated to each of the data services prior to transmitting the video signal. The video signal is separated into the separate data services without field or line windowing. Every pair of biphase elements occurring after the start code is checked for anticoincidence errors, and all wanted bits are stored in a buffer memory. The wanted bits are transferred from the buffer memory to an output memory only when no anticoincidence error has occurred between the start code and the last wanted bit.

Abstract: In order to achieve a greater degree of security in the decoder for the control frame of teletext pages, the control frame is initially selected and decoded from the data stream by means of a bit by bit comparison with a frame word. Thereby, the following steps are carried out in dependence on the number of coincidences occurring during the bit by bit comparison with the frame word:a) if, during the bit by bit comparison, eight coincidences are detected, the control frame is considered to have been identified and the counter is reset;b) if less than eight coincidences are detected, it is determined whether a particular number ("444") or a multiple of this number ("n 444") has been reached on the basis of the count-state of the clock pulse counter, whereby, in the event that this number has been reached, the control frame is considered to have been identified and the counter is reset.

Abstract: A cordless telephone system includes a single base unit and at least two remote handunits, where the base unit employs two transmitter channels coupled together through a low impedance and coupled to a single antenna. The transmitter channels include voltage controlled crystal oscillators (VCXOs) and frequency tripler circuitry, rather than PLLs in order to keep intermodulation distortion at the outputs of the transmitter amplifiers to a minimum.

Abstract: A band switchable double tuned circuit having a balanced secondary is presented. A primary tunable tank circuit with a plurality of first inductances is tuned to a first frequency by a first capacitor coupled in parallel with the first inductances. A secondary tank circuit with a plurality of second inductances inductively coupled to ones of the first inductances has a second capacitor coupled in parallel with the second inductances for tuning the secondary to the first frequency. The DC reference potential for the secondary circuit, is coupled to a nodal junction of the plurality of second inductances with the secondary tank circuit providing a balanced signal output. At least one of the plurality of first inductances and the second inductances are switchable for bandswitching the tuning of the primary and secondary tank circuits to a second frequency.

Abstract: An auxiliary video information decoder for decoding information such as closed caption data in a video signal identifies a desired horizontal line of video in a video signal. A reference pulse in a synchronizing signal is detected followed by the generation of first and second window pulse signals occurring at predetermined delays after detection of the reference pulse. A pulse occurring in the synchronizing signal during the window pulses indicates the start of the desired horizontal line interval. A field identification signal may also be generated. Features for improving noise and phase error immunity when identifying a video line are provided.

Abstract: A system for processing a television signal including a data component, such as extended data services data, includes a decoder for processing the data component to provide data representing time information. A control device responds to the data for modifying time information, e.g., time of day, that is maintained in the system. The time information decoded from the video signal is compared to the time information maintained in the system to determine a time difference. If the time difference is in a predetermined range, the time difference indicates that the time information from the television signal is invalid. The control device responds to the time difference being in the predetermined range by preventing modification of the time information maintained in the system. A user may provide an input via a device such as a remote control to control the manner in which the control device responds to the time difference.

Abstract: When film is transmitted by television, the same frame of film is used to generate both interlace television fields. This results in the information carried by the second field being temporally displaced from the original by 20 ms. This displacement gives rise to judder and double image artifacts in the received image. To overcome these defects the intermediate fields are generated from the original film frames by double sided motion compensated interpolation wherein the motion information is calculated using double sided block matching. The invention may be applied either in a television receiver or video signal decoder or in the television studio before the television signal is transmitted.

Abstract: An IR repeater is disclosed which is resistant to CFL interference. The IR repeater includes a receiver section for receiving an IR light signal representing a coded signal modulated by a modulating signal, and for detecting the coded signal. An oscillator generates a transmitter modulating signal, and a transmitter section, coupled to the receiver section and the oscillator, generates an IR light signal representing the detected coded signal modulated by the transmitter modulating signal.

Abstract: In a quadrature FM detector, demodulation is performed by a product detector which multiplies an amplitude limited FM modulated information signal by a version of the amplitude limited FM modulated information signal which has been phase shifted by a phase shifting network including a single tuned LC circuit. In order to assure that the LC circuit is tuned to the carrier frequency of the FM signal, the LC circuit is tuned by a variable impedance device in response to a control signal generated by a bus controlled DAC. The control signal is coupled to the variable impedance device at the same pin of an integrated circuit where the LC circuit is coupled to the demodulator.

Abstract: Audio bus receiver includes a pair of bipolar transistors each having a base coupled via a respective resistor to a respective bus receiver input terminal, each having an emitter that is diode coupled to a respective current source and each having a collector coupled via a respective load resistor to a source of reference potential. The emitters are coupled together via a gain control resistor and the collectors are coupled to an output terminal via a differential amplifier. Advantageously, the receiver avoids loading the bus under power-down conditions without requiring the use of stand-by power supplies. Additionally, high common mode rejection is achieved without need for precision matching of components and only a single supply voltage is required for operation.

Abstract: The present invention provides for an analog and/or digital radio broadcast transmission system and radio receiver therefor, which includes a control signal having an item of control information concerning another, different type of transmission/receive system. The receiver is a hybrid receiver able to receive both types of signals. When the same program material is available on both of the different systems, the control signal is used for switching the different systems so that the receiver receives the program on the system which provides the best reception.

Abstract: A voltage regulator is switchable between a lower regulated DC output voltage and a higher regulated DC output voltage. Foldback current limiting is actuated in response to the current drawn by the load when a current limiting threshold is exceeded. The current limiting threshold is determined by the voltage relationship at respective taps of a pair of voltage dividers, with said relationship being effected by the voltage appearing across a current sensing resistor coupled in series with the load. The current limiting threshold is adjusted to be approximately the same for both the lower and the higher regulated DC output voltages. This adjustment is accomplished with a non-linear voltage dependent device, which is coupled to one of the voltage dividers, and is actuated in the higher output voltage mode.

Abstract: A subtractor (106) forms a difference signal (D) from a video input signal (C) and a further signal (M) supplied thereto. The difference signal is limited (108) and attenuated (110) and the resultant signal (F) is combined (112) with the video input signal for providing a noise reduced video output signal (H). A delay circuit (202), responsive to the video output signal, provides field (A) and frame (B) delayed video signals. A selection circuit (220) selects a median value (M) of the field delayed video signal, the frame delayed video signal and the video input signal as the further signal for application to the subtractor. Advantageously, the further signal provides the dual functions of (1) facilitating the noise reduction of the output signal and (2) concurrently reducing the occurrence of potential motion artifacts to a very substantial degree.

Abstract: A video signal processing system, such as a pay TV system, that includes a smart card access control feature decodes control information from data included in groups of video line intervals that represent data channels. Each channel includes data arranged in packets of data. Each packet includes both descriptor data and application data. The packets of data are extracted from the video lines by a data dispatcher. After receiving a packet from a data channel, the data dispatcher analyses the descriptor data to determine the target for the application data. The data dispatcher transmits the application data contained in the packet, without analyzing the data, to the correct target processor unit, e.g. either a control access processor or a decoder intelligent processor. Information that may be transferred to the decoder processor includes, a specific channel allocation table, data related to the VTR of the customer, and information related to a geographic location.

Abstract: The present invention concerns a voltage regulator wherein the series pass transistor and an amplification transistor are of complementary types. Supply current flows from the DC supply source through the emitter-collector path of the series pass transistor to the load. The amount of this current is controlled by a negative feedback control signal coupled from the regulated output voltage to the base electrode of the amplification transistor, which in turn drives the base of the series pass transistor. The emitter electrode of the amplification transistor is coupled to a voltage which is less than the regulated DC output voltage so that drive requirements for the pair of transistors is reduced.

Abstract: A reset signal generator includes circuitry for detecting conditions indicating that a reset signal is necessary and generating a reset signal in response. Such conditions may include low power supply voltage (i.e., "brown out") or the presence of transient signal spikes. Circuitry is provided for extending the duration of the reset signal after power is initially applied, because at this time associated digital circuitry may not be fully powered-up, and may require a longer than normal reset pulse. In contrast, a reset pulse of a normal duration is generated when the digital circuitry is fully powered-up and a transient signal spike is detected. Isolating circuitry is coupled between the detecting circuit and the extending circuit to isolate the detecting circuit from the extending circuit when there is no power-on condition, (i.e. when normal operating voltage is present) in order to prevent the duration of the reset pulse from being extended.