Abstract: A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem) is associated with each PE and contains local PE instructions for execution on the local PE. Local PE Imem fetch, decode, and execute logic are associated with each PE. Instruction path selection logic in each PE is used to select between control processor distributed instructions and local PE instructions fetched from the local PE Imem. Each PE is also initialized to receive control processor distributed instructions. In addition, local hold generation logic is associated with each PE. A PE receiving a Tstart instruction causes the instruction path selection logic to switch to fetch local PE Imem instructions.

Abstract: The invention relates to a transporting device for patients who are to be transported from a first site to a second site using low force. For this purpose is provided a firm board which can also be resilient, wherein this board is encompassed by an endless band. This endless band is adapted to the shape of the board and can slide around the board. The outer ends of the board are provided with caps which, on the one hand, lend the board high rigidity at the ends and, on the other hand, prevent body fluids from penetrating into the interspace between board and endless band.

Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

Abstract: Methods and computer readable medium for collaborating on geographical maps between two or more computers are disclosed. In particular, sharing a geographical location on a map between two or more computers and co-navigating a map between two or more computers are disclosed. With respect to sharing a geographical location, the geographical location is retrieved to the first computer. The geographical location is added to the map being rendered at the first computer and is sent to a second computer. A map including the geographical location is rendered at the second computer. With respect to co-navigating, a map is displayed from a map perspective at the first computer. The map perspective is sent to the second computer. A map from the same map perspective being displayed at the first computer is rendered at the second computer.

Abstract: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.

Abstract: Techniques for providing cost effective and tamper evident prepaid card packaging are described. By forming a cutout in a panel of the prepaid card packaging, covering the cutout with a material such as red glassine, and aligning an activation bar code or other indicia on the card with the cutout when mounting the card within the packaging, the security of the activation indicia can be better maintained. After purchase, the bar code can be scanned through the red glassine but prior to purchase, the red glassine prevents photocopying.

Abstract: Techniques for light emitting diode (LED) lighting with heat spreading in illumination gaps. Inexpensive structural aluminum may be suitably employed to form a passive heat spreading mount for plural LEDs whose illumination collectively combines to provide the light needed by a particular lighting fixture, such as a pendant chandelier, by way of example, by angling fins of the passive heat spreading mount to correspond to illumination gaps of the LEDs.

Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

Abstract: A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters to the multi-cycle state machines, to fetch operands from a node's memory, and to control the transfer of results from the multi-cycle state machines.

Abstract: Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

Abstract: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: A scalable fulfillment system is presented that supports business processes, manages the transport and processing of business-related messages or documents between a business entity and clients, such as customers, vendors, and business partners, and generally supports business document processing. The system intelligently manages the transportation of files from clients, through processing of files, to generating responses that return to the clients. To accommodate a heterogeneous interfacing and processing with different clients in a central system, a file normalization technique is used that captures a common meta-data format from the numerous heterogeneous file types used by numerous clients. The meta-data files, also referred to as messages, contain links to their associated data files and are processed separately.

Abstract: Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. In one technique, an address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable translating of the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power. Address translation functions are shown to be useful for vector operations and a new type of storage unit using built in address translation functions is presented.

Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.

Abstract: Methods and computer readable medium for collaborating on geographical maps between two or more computers are disclosed. In particular, sharing a geographical location on a map between two or more computers and co-navigating a map between two or more computers are disclosed. With respect to sharing a geographical location, the geographical location is retrieved to the first computer. The geographical location is added to the map being rendered at the first computer and is sent to a second computer. A map including the geographical location is rendered at the second computer. With respect to co-navigating, a map is displayed from a map perspective at the first computer. The map perspective is sent to the second computer. A map from the same map perspective being displayed at the first computer is rendered at the second computer.

Abstract: A system which allows identification of a consumer as belonging to a designated category and makes special offers available to consumers who are members of the designated category is described. The system comprises a database of offers accessible through connection by consumer operated computers upon authentication of consumer registration, an offer presentation module for controlling access to the database of offers and a consumer registration module allowing registration of a consumer for access to the database of offers. The consumer registration module allows registration of a consumer upon submission of identifying information provided to the consumer by a party who has identified the consumer as belonging to a designated category and used to identify the consumer as belonging to the designated category.

Abstract: A trouble diagnosis device of a vehicle body acceleration sensor by determining that the output fixing trouble of the vehicle body acceleration sensor or the like is not generated at a point of time that the fluctuation width of the output value of a vehicle body acceleration sensor becomes a predetermined value or above during the traveling of the vehicle with the vehicle speed equal to or more than the predetermined speed, and by stopping the trouble diagnosis of the output fixing trouble of the vehicle body acceleration sensor or the like until the vehicle speed is lowered to a value less than the predetermined speed thereafter, it is possible to avoid the trouble diagnosis of the output fixing trouble of the vehicle body acceleration sensor or the like when that the trouble diagnosis of the output fixing trouble of the vehicle body acceleration sensor or the like is unnecessary.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.