Patents Represented by Attorney Priest & Goldstein, PLLC
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Patent number: 7853779Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.Type: GrantFiled: May 14, 2008Date of Patent: December 14, 2010Assignee: Altera CorporationInventors: Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek, Larry D. Larsen
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Patent number: 7852953Abstract: Power allocation methods for multiuser orthogonal frequency division multiplexing (OFDM) are described. Arbitrary partitioning of the OFDM tones among users and arbitrary modulation formats, possibly different for every user, are considered. Two systems of receivers and transmitters and corresponding methods address power allocation, respectively for slow fading channels tracked instantaneously by the system and for fast fading channels known only statistically thereby.Type: GrantFiled: March 30, 2006Date of Patent: December 14, 2010Assignee: Alcatel-Lucent USAInventor: Angel Lozano
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Patent number: 7836317Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.Type: GrantFiled: January 29, 2008Date of Patent: November 16, 2010Assignee: Altera Corp.Inventors: Patrick R. Marchand, Gerald George Pechanek, Edward A. Wolff
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Patent number: 7822779Abstract: A scalable fulfillment system is presented that supports business processes, manages the transport and processing of business-related messages or documents between a business entity and clients, such as customers, vendors, and business partners, and generally supports business document processing. The system intelligently manages the transportation of files from clients, through processing of files, to generating responses that return to the clients. To accommodate a heterogeneous interfacing and processing with different clients in a central system, a file normalization technique is used that captures a common meta-data format from the numerous heterogeneous file types used by numerous clients. The meta-data files, also referred to as messages, contain links to their associated data files and are processed separately.Type: GrantFiled: April 23, 2004Date of Patent: October 26, 2010Assignee: Wal-Mart Stores, INc.Inventors: Alvin Kai-Hau Chang, Simon Wing-Lok Hui, Yulia Groza, Nathaniel D. Harward, Steven S. Chen
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Patent number: 7809932Abstract: Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes.Type: GrantFiled: March 22, 2004Date of Patent: October 5, 2010Assignee: Altera CorporationInventors: Edwin Franklin Barry, Gerald George Pechanek, Patrick R. Marchand
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Patent number: 7805048Abstract: Sideways emission enhancements are described for light emitting diode (LED) lighting solutions having a wide variety of applications. While a typical LED lighting device has a substantial portion of its light emitted near a normal to the semiconductor photonic chip emitting the light, the present approach may suitable provide a compact, easily manufacturable device with good thermal design characteristics and a changed emission pattern without changing the horizontal mounting plane of the semiconductor photonic chip.Type: GrantFiled: May 10, 2006Date of Patent: September 28, 2010Assignee: Cree, Inc.Inventors: Ban P. Loh, Nicholas Medendorp
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Patent number: 7794114Abstract: A solid state lighting subassembly or fixture includes an anisotropic heat spreading material. A heat spreading layer may be placed between a light emitting diode (LED) and luminaire or reflector and serves to spread heat laterally away from the LED. Low profile, low weight heat spreading may be utilized both to retrofit existing light fixtures with LEDs or to replace existing incandescent and fluorescent fixtures with LED based fixtures.Type: GrantFiled: October 11, 2006Date of Patent: September 14, 2010Assignee: Cree, Inc.Inventor: Nicholas W. Medendorp, Jr.
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Patent number: 7779983Abstract: A two door electronic safe is described wherein a bill acceptor, as well as other electronic control circuitry, and a banknote canister are partitioned in first and second compartments with access by first and second access doors, respectively, so that a service call can be made to service the bill acceptor or other electronics without having to allow access to the banknote canister thereby facilitating service calls and allowing the separation of the service call function from the cash collection function.Type: GrantFiled: March 12, 2009Date of Patent: August 24, 2010Assignee: Ellenby Technologies, Inc.Inventor: Bob M. Dobbins
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Patent number: 7765338Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FET computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.Type: GrantFiled: July 9, 2007Date of Patent: July 27, 2010Assignee: Altera CorporationInventors: Edwin Franklin Barry, Nikos P. Pitsianis, Kevin Coopman
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Patent number: 7756347Abstract: Techniques for performing the processing of blocks of video in multiple stages. Each stage is executed for blocks of data in the frame that need to go through that stage, based on the coding type, before moving to the next stage. This order of execution allows blocks of data to be processed in a nonsequential order, unless the blocks need to go through the same processing stages. Multiple processing elements (PEs) operating in SIMD mode executing the same task and operating on different blocks of data may be utilized, avoiding idle times for the PEs. In another aspect, inverse scan and dequantization operations for blocks of data are merged in a single procedure operating on multiple PEs operating in SIMD mode. This procedure makes efficient use of the multiple PEs and speeds up processing by combining two operations, inverse scan (reordering) and dequantization, which load the execution units differently.Type: GrantFiled: February 5, 2007Date of Patent: July 13, 2010Assignee: Altera CorporationInventors: Doina Petrescu, Trampas Stern, Marco Jacobs, Dan Searles, Charles W. Kurak, Jr.
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Patent number: 7743983Abstract: Systems and techniques for locating designated electronic shelf labels. A locator device transmits commands to a designated label, causing a label to take on distinctive characteristics, for example showing a characteristic display. Alternatively or in addition, the locator device detects transmissions from labels within range and provides an indication, such as an audible tone or a serial number display, when an identified label is within range. A user may enter a serial number of one or more labels using a keypad, or may upload one or more serial numbers to the locator device. The user then moves with the locator device around a location where labels are in use. Depending on the design of the device, the device broadcasts commands to labels to cause the labels to take on identifiable characteristics, detects serial numbers of labels based on transmissions from labels within range, or both.Type: GrantFiled: November 22, 2005Date of Patent: June 29, 2010Assignee: NCR CorporationInventor: Cheryl Kay Harkins
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Patent number: 7744266Abstract: Socket arrangements for releasably mounting LEDs and light fixtures or assemblies employing such sockets are described. The socket arrangements facilitate the replacement of LEDs to replace an original LED with a brighter replacement, to change the color of the LED, to replace a single LED with a multiple chip LED, to replace a damaged or burned out LED with a new one, or the like. In further assemblies with plural LEDs, the use of ready release sockets facilitates selective replacement of an LED or LEDs and greatly enhances the flexibility of such units.Type: GrantFiled: April 30, 2009Date of Patent: June 29, 2010Assignee: Cree, Inc.Inventors: Robert Edward Higley, Faramarz Hafezi
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Patent number: 7716123Abstract: Systems and methods are described for automatically processing mortgage insurance claims. In one described system, a central server computer receives inputs from, and provides outputs to, a servicer terminal connected into a network. The servicer terminal captures data from a servicer submitting a mortgage insurance claim. A claims database is connected into the network, containing data relating to the mortgage insurance claim. A claim audit rulebase is connected into the network, for automatically performing an audit and adjustment of the submitted mortgage insurance claim. The system automatically provides results of the audit and adjustment to the servicer at the servicer terminal, and presents the servicer with an option to interact with a claim representative to resolve any issues.Type: GrantFiled: December 21, 2001Date of Patent: May 11, 2010Assignee: GE Mortgage Holdings, LLCInventors: Nancy J. Dodd, Charla M. Parker, Allison N. Pope, Joanne A. Stewart, Traci L. Whitney, Robert Johnston
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Patent number: 7698202Abstract: Techniques for more accurately estimating the risk, or active risk, of an investment portfolio when using factor risk models are disclosed. This improved accuracy is achieved by identifying and compensating for the inherent “modeling error” present when risk is represented using a factor risk model. The approach adds one or more factors that depend on the investment portfolio and that explicitly compensate for factors that are unspecified or unattributed in the original factor risk model. These unspecified factors of the original factor risk model lead to modeling error in the original factor risk model. The approach can be used with a variety of different factor risk models, such as, fundamental, statistical and macro risk models, for example, and for a variety of securities, such as equities, international equities, composites, exchange traded funds (ETFs), or the like, currencies, and fixed-income, for example.Type: GrantFiled: January 29, 2007Date of Patent: April 13, 2010Assignee: Axioma, Inc.Inventors: Robert A. Stubbs, Stefan Hans Schmieta
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Patent number: 7690802Abstract: An LED based emergency lighting system is described. Unlike a typical approach in which one lighting system provides normal ambient lighting and a second different system provides auxiliary emergency lighting, a common integrated system can be satisfactorily employed.Type: GrantFiled: April 17, 2007Date of Patent: April 6, 2010Assignee: Cree, Inc.Inventors: Robert Edward Higley, Mark Terrence McClear
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Patent number: 7688951Abstract: Problems are proactively analyzed and responded to as they are detected in a virtual private network (VPN) access path rather than waiting for a user to manually report the problem. When a problem is automatically detected, such as a failure causing degraded performance, an alarm may be generated. The alarm proactively triggers rules-based analysis procedures and isolation testing to diagnose problem in a VPN access path. Based on the testing and analysis, a comprehensive trouble ticket may be generated that is customized with specific alarm information allowing for increased efficiency in problem isolation and saving significant time and resources in resolving the problem.Type: GrantFiled: December 22, 2005Date of Patent: March 30, 2010Assignee: AT&T Intellectual Property II, L.P.Inventors: Paritosh Bajpay, Roberta A. Bienfait, Mojgan Dardashti, Hossein Eslambolchi, Jackson Liu, John McCanuel, Zhiqiang Qian, Michael J. Zinnikas
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Patent number: 7681431Abstract: A method of calibrating a scale which enforces exercise requirements. The method includes causing an interface to provide a first indication to place weight on the scale by control circuitry of the scale, receiving weight signals from a load cell by the control circuitry, causing the interface to provide a second indication that exercising has begun and of the level of weight applied by the control circuitry, determining that a minimum recommended calibration weight has been placed on the scale by the control circuitry, and causing an interface to provide a third indication that the minimum recommended calibration weight has been placed on the scale by the control circuitry.Type: GrantFiled: April 12, 2007Date of Patent: March 23, 2010Assignee: NCR CorporationInventors: John P. Roquemore, III, Donald A. Collins, Jr.
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Methods and apparatus for a scanner having a top plate assembly with weight measurement capabilities
Patent number: 7681795Abstract: Systems and techniques for a scanner having a top plate with an integrated scale. A scanner base mates with a scanner top plate assembly, with the top plate assembly including an integrated scale. The top plate assembly includes a scan window and a scale mechanism. The top plate rests on or is secured to suitable resting points in the scanner base. The top plate suitably receives power, and communicates measurement data to the scanner base, without the use of cables or other connectors whose weight may interfere with accurate reading of weight. A scanner base may be designed so as to accommodate any of a variety of alternative scanner top plate types without reconfiguration, or with a relatively simple reconfiguration of the scanner base.Type: GrantFiled: March 27, 2006Date of Patent: March 23, 2010Assignee: NCR CorporationInventor: Pete Roquemore -
Patent number: RE41703Abstract: A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization.Type: GrantFiled: June 21, 2004Date of Patent: September 14, 2010Assignee: Altera Corp.Inventors: Gerald George Pechanek, Thomas L. Drabenstott, Juan Guillermo Revilla, David Strube, Grayson Morris
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Patent number: RE41904Abstract: Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical processing element (PE) identifier translation is employed in conjunction with a ManArray PE interconnection topology to support a variety of communication models, such as hypercube and such. Also, PE addressing nodes are based upon logically nested parameterized loops. Mechanisms for updating loop parameters, as well as exemplary instruction formats are also described.Type: GrantFiled: September 22, 2006Date of Patent: October 26, 2010Assignee: Altera CorporationInventor: Edwin Franklin Barry