Abstract: Provided is a method for the in vitro aseptic mass production and sporulation of arbuscular mycorrhizal fungi (AMF). The method comprises providing symbiotic root organs with AMF propagules and spores after the root organs are inoculated with AMF inoculums in advance to form AMF propagules in the root organs and cultivating them in an aseptic container, and then providing the whole symbiotic root organs and AMF propagules with liquid medium for a temporary contact between the liquid medium and the root organ with AMF propagules in order to cultivate AMF, then removing the liquid medium from the symbiotic root organs and arbuscular mycorrhizal fungal propagules and finally repeating former two steps periodically to facilitate the mass production and sporulation of the arbuscular mycorrhizal fungi.

Abstract: Scissors for angularly cutting sheet stock is disclosed. The scissors comprises oblique slots in a lower handle, fasteners in the oblique slots, a rear elongate slot in a lower ridge of a board, and a pin slidably defined in the elongate slot. In a closed state, fasteners are slid to a lowest point in the oblique slot to be urged by the ridge so that the ridge is prevented from further rearward movement with energy stored in a resilient piece. In a cutting operation press the lower and the upper handles against each other for causing the board and the blade to close on the sheet stock. The ridge pivots in response to pivoting the lower handle. Pin slides along the elongate slot to move the ridge. A rear portion of the board moves upward. A pointed end of the blade closes on a forward end of the board.

Abstract: A fastening structure for securing a stator of a motor includes a copper sleeve with a notch thereon and a fastener. The fastener is composed of a position section and a hook section, wherein the hook section engages with the notch and the position section presses on the top surfaces of the coil bobbin of the stator.

Abstract: A stacked-gate cell structure having a tapered floating-gate layer and a laterally graded source/drain diffusion profile is implemented to form NAND cell strings over a self-aligned STI structure having a high coupling ratio. The paired string select lines and the paired ground select lines being formed over one-side tapered floating-gate layers are simultaneously defined by a spacer formation technique and are therefore scalable. Each of common-source conductive bus lines is formed over a first flat bed between a pair of sidewall dielectric spacers being formed over sidewalls of the paired ground select lines. A plurality of planarized common-drain conductive islands are formed over common-drain diffusion regions between another pair of sidewall dielectric spacers being formed over sidewalls of the paired string select lines and are patterned simultaneously with a plurality of metal bit-lines by using a masking photoresist step.

Abstract: A mechanism for positioning a substrate of an image sensor. The substrate has first to fourth edges. The mechanism includes a standard unit, a link unit, and a push-up needle unit. The standard unit has adjacent first and second standard planes, both of which define a positioning region for receiving the substrate. The first and second edges contact the first and second standard planes, respectively. The link unit includes a first link and a second link pivotally mounted to the first link at a pivotal portion for positioning the third edge of the substrate. The push-up needle unit positions the fourth edge. When the link unit operates, the push-up needle unit and the pivotal portion of the link unit are moved toward the fourth edge and the third edge of the substrate, respectively, to position the substrate.

Abstract: A combination puzzle toy includes a case defining a top open chamber having a flat bottom surface, and a plurality of blocks to be inserted into the top open chamber and supported on the flat bottom surface of the top open chamber and coupled to one another in a flush manner to form one of a number of combinations, each block being formed of a flat rectangular first block member and a flat rectangular second block member asymmetrically fixedly arranged in a stack.

Abstract: A method for manufacturing an image sensor includes the steps of: providing a substrate having an upper surface and a lower surface; mounting a frame layer to the upper surface of the substrate to form a cavity together with the substrate; mounting a photosensitive chip to the upper surface of the substrate and within the cavity; providing a plurality of wires to electrically connect the photosensitive chip to the substrate; supplying an adhesive layer to the upper surface of the substrate and within the cavity; mounting a transparent layer to the frame layer to cover the photosensitive chip; and illuminating an electrostatic-charge eliminating light source on the transparent layer to let particles within the cavity fall down to the adhesive layer.

Abstract: A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.

Abstract: A scaled MOSFET device of the present invention comprises a shallow-trench-isolation structure being formed on a semiconductor substrate; a conductive-gate structure having a pair of second conductive sidewall spacers formed over each inner sidewall of a gate region and on a first conductive layer and first raised field-oxide layers for forming an implant region in a central portion of a channel and a planarized third conductive layer for forming a salicide-gate structure or a polycide-gate structure; a buffer-dielectric layer being formed over each sidewall of the conductive-gate structure for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-dielectric layers for forming heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a self-aligned silicidation contact over each of the heavily-doped source/drain diffus

Abstract: An image sensor having shortened wires. The image sensor includes a substrate composed of metal sheets arranged in a matrix, a photosensitive chip, bonding pads on the chip, a frame layer, wires and a transparent layer placed on the frame layer. Each metal sheet has a first board and a second board. A chamber is defined under the substrate to accommodate the chip. Each pad is arranged between first boards. The frame layer is formed on a periphery and the bottom surface to encapsulate the chip. The bottom faces of the second boards are electrically connected to a printed circuit board. Each wire has a first terminal and a second terminal. The first terminals are electrically connected to the pads, and the second terminals are electrically connected to the first boards, respectively.

Abstract: An apparatus for electrode charge machining includes a T-shaped quill movable in the vertical direction, at least two linear motor yokes attached to the quill symmetrical about the fixed point of the piston rod of a counter balance device and moving in parallel, at least two linear motor permanent magnets facing the yokes, an electrode mounting device fixed at the lower end of the quill, the counter balance device for balancing a gravitational force acting on the quill and the tool electrode. The gravity balance device consists of an air cylinder with the piston rod. And the air cylinder is fixed with a support frame, with the piston rod extending down into the quill and fixed with a level plate in the quill in the coaxially with the quill.

Abstract: A stack-gate non-volatile memory device with a tapered floating-gate structure is disclosed by the present invention, in which the tapered floating-gate structure offers a longer effective channel length to alleviate the punch-through effect and a larger surface area for erasing or programming between the tapered floating-gate structure and the integrated common-source/drain conductive structure. The stack-gate non-volatile memory devices of the present invention are implemented into three contactless array architectures: a contactless NOR-type array, a contacless NAND-type array, and a contactless parallel common-source/drain conductive bit-lines array. The features and advantages of the contactless memory arrays are a smaller cell size of 4F2, a smaller common-source/drain bus-line resistance and capacitance, a higher erasing speed, and a smaller bit/word-line resistance and capacitance, as compared to the prior arts.

Abstract: A water pump motor is constructed to include a housing, the housing having a conical water guide chamber gradually expanding from the top side toward the bottom side, water inlets around the periphery for guiding water into the water guide chamber, and an air passage for guiding air into the water guide chamber to mix with water, a vane wheel fastened to a motor shaft inside the housing and suspended in the water guide chamber, the vane wheel having triangular vanes radially arranged at the top around the motor shaft, a hollow water outlet pipe holder coupled to the bottom shell to hold a water outlet pipe, the water outlet pipe holder having radial dampers equiangularly spaced around the inside wall to guide water toward the water outlet pipe.

Abstract: The stack-type DRAM memory structure of the present invention comprises a plurality of self-aligned thin third conductive islands over shallow heavily-doped source diffusion regions without dummy transistors to obtain a cell size of 6F2 or smaller; a rectangular tube-shaped cavity having a conductive island formed above a nearby transistor-stack being formed over each of the self-aligned thin third conductive islands to offer a larger surface area for forming a high-capacity DRAM capacitor of the present invention; a planarized third conductive island being formed between a pair of first sidewall dielectric spacers and on each of shallow heavily-doped common-drain diffusion regions to offer a larger contact area and a higher contact integrity; and a plurality of planarized conductive contact-islands being formed over the planarized third conductive islands to eliminate the aspect-ratio effect and being patterned and etched simultaneously with a plurality of bit lines.

Abstract: A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6 F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.

Abstract: A dual-bit floating-gate flash cell structure comprises a gate region being formed between a common-source region and a common-drain region. The gate region comprises a pair of floating-gates being defined by a pair of second sidewall dielectric spacers and a select-gate dielectric layer being formed between the pair of floating-gates. The common-source/drain region comprises a common-source/drain diffusion region or a pair of isolated source/drain diffusion regions being divided by a shallow trench isolation formed between a pair of first sidewall dielectric spacers. A word line being formed over an intergate dielectric layer is at least formed over the pair of floating-gates and the select-gate dielectric layer. Based on common-source/drain diffusion regions and isolated source/drain diffusion regions of the dual-bit floating-gate cell structure, two different contactless flash memory arrays are formed.

Abstract: A rear pushbutton type switch arrangement for flashlight formed of an aluminum alloy barrel holding a battery set and a lamp assembly, an electrically conducting rotary rear cap provided at a rear side of said barrel and a switch structure is disclosed. The switch structure has an externally threaded, electrically conducting, hollow, cylindrical metal casing connected between the barrel and the rotary cap to hold the other parts of the switch structure firmly in the rotary rear cap so that the other parts of the switch structure do not fall from the rotary rear cap when disconnected from the barrel for a replacement of the battery set.