Patents Represented by Attorney Quintero Law Office
  • Patent number: 7755143
    Abstract: A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: July 13, 2010
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning Jou, Geeng-Lih Lin
  • Patent number: 7754056
    Abstract: A biosensor containing ruthenium, measurement using the same, and the application thereof. The biosensor comprises an extended gate field effect transistor (EGFET) structure, including a metal oxide semiconductor field effect transistor (MOSFET), a sensing unit comprising a substrate, a layer comprising ruthenium on the substrate, and a metal wire connecting the MOSFET and the sensing unit.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: July 13, 2010
    Assignee: National Yunlin University of Science and Technology
    Inventors: Jung-Chuan Chou, Shih-I Liu
  • Patent number: 7754614
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: July 13, 2010
    Assignee: Nanya Technologies Corporation
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Patent number: 7745726
    Abstract: An assembly structure is provided. The assembly structure includes a first substrate, a second substrate and a medium layer disposed between the first and second substrates. The medium layer includes a side edge, and the second substrate includes at least one lead wire. When the second substrate is disposed on the medium layer, the lead wire of the second substrate is relatively oblique to the side edge of the medium layer.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: June 29, 2010
    Assignee: Raydium Semiconductor Corporation
    Inventors: Ming-Te Lin, Chin-Yung Chen
  • Patent number: 7746540
    Abstract: Electrowetting display devices and fabrication methods thereof are presented. The electrowetting display device includes a first substrate and a second substrate with a polar fluid layer and a non-polar fluid layer insolvable to each other and interposed between the first and second substrates. A first transparent electrode is disposed on the first substrate. A second electrode is disposed on the second substrate. A dielectric layer is disposed on the second electrode. A hydrophilic partition wall structure is directly disposed on the dielectric layer defining a plurality of pixel regions. A layer of low surface energy material is disposed on the dielectric layer within each of the pixel region.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: June 29, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Lung Lo, Chih-Chun Hsiao
  • Patent number: 7746364
    Abstract: A brightness correction method for a display panel, comprising showing a plurality of image areas in the display panel, wherein the image areas display different colors, each color has a plurality of luminance values according to a plurality of gray values, and wherein each gray value corresponds to a gamma voltage; detecting the luminance values; and adjusting the gamma voltages according to the detected luminance values.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: June 29, 2010
    Assignee: Getac Technology Corporation
    Inventors: Chang-Han Shen, Chih-Fu Yang
  • Patent number: 7745343
    Abstract: A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer are sequentially formed. A bond pad is formed over the second interlayer dielectric layer in a second device region of the semiconductor structure. A passivation layer is formed over the bond pad and the second interlayer dielectric layer. A first etching process is performed to form a first opening in the first device region and a second opening in the second device region, wherein the first opening exposes a portion of the second interlayer dielectric layer over the fuse element and, and the second opening partially exposes a portion of the bond pad. A second etching process and a third etching process are performed to leave another passivation layer conformably covering the fuse element and the semiconductor structure adjacent thereto.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: June 29, 2010
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsun Lo, Hsing-Chao Liu, Jin-Dong Chern, Kwang-Ming Lin
  • Patent number: 7745811
    Abstract: Phase change memory devices and methods for fabricating the same. An exemplary phase change memory device includes a conductive element formed in a dielectric layer. A phase change material layer is formed in the dielectric layer. A conductive layer extends in the dielectric layer to respectively electrically connect the phase change layer and a sidewall of the conductive element.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: June 29, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Hengyuan Lee, Der-Sheng Chao
  • Patent number: 7739760
    Abstract: A bedstead assembly includes a support frame and a top plate unit disposed on the support frame. The support frame includes a rectangular foldable frame member convertible between unfolded and folded states. The foldable frame member includes a plurality of parallel non-foldable plates and a plurality of pairs of foldable plates. Any two adjacent non-foldable plates interconnect pivotally one corresponding pair of foldable plates to define a void space when the foldable frame member is in the unfolded state. The void spaces in the foldable frame member are arranged along a direction parallel to the foldable plates. Pivotable plate portions of the foldable plates are perpendicular to the non-foldable plates when the foldable frame member is in the unfolded state, and are parallel to the non-foldable plates when the foldable frame member is in the folded state.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: June 22, 2010
    Inventors: Cheng-Chung Wang, Kenneth Wang
  • Patent number: 7741169
    Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: June 22, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Shin-Chii Lu, Yu-Ming Lin, Min-Hung Lee, Zing-Way Pei, Wen Yi Hsieh
  • Patent number: 7740759
    Abstract: A magnetic separation device separating magnetic material from a working fluid of a container is disclosed. The magnetic separation device includes a first element, a second element and a magnetic assembly structure including a plurality of magnetic units. The first element includes a first body, a plurality of first main positioning portions disposed on the first body, and a plurality of first sub-positioning portions disposed on the first body and next to the first main positioning portions to receive the container. The second element includes a second body, a plurality of second main positioning portions disposed on the second body, and a plurality of second sub-positioning portions disposed on the second body and next to the second main positioning portions to receive the container. The magnetic units disposed on the first main positioning portions and the second main positioning portions absorb magnetic material from the working fluid.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: June 22, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chih Hsien Su, Hsiao Cheng Lin, Chi-Min Chau, Yuh-Jiuan Lin, Wen-Hsun Kuo
  • Patent number: 7741822
    Abstract: The invention provides DC-DC converters comprising a load sensor, a variable Power MOS, and a Power MOS width controlling and driving device. The Power MOS width controlling and driving device is coupled between the load sensor and the variable Power MOS. The variable Power MOS comprises a plurality of PMOS transistors coupled in parallel and a plurality of NMOS transistors coupled in parallel. After the load sensor detects the load current of the DC-DC converter, the Power MOS width controlling and driving device conducts the PMOS and NMOS transistors according to the sensed load current to control the total size of the conduction paths that couple a transformed DC voltage output terminal to a source of an original DC voltage or ground.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: June 22, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Ke-Horng Chen, Sy-Yen Kuo, Hong-Wei Huang, Ruei-Ming Gan
  • Patent number: 7739763
    Abstract: An inflatable bed includes a bedstead assembly, a mattress assembly, and an electrical air pump unit. The mattress assembly is disposed on and above the bedstead assembly, and includes a top sheet, a bottom sheet disposed under the top sheet, and a plurality of surrounding sheets interconnecting the top and bottom sheets to form a plurality of air chambers, which are not in fluid communication with each other. Each of the air chambers is defined among the top sheet, the bottom sheet, and a respective one of the surrounding sheets. The electrical air pump unit is disposed on the bedstead assembly, and is operable to inflate the air chambers individually so that air pressures in the air chambers may be different.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: June 22, 2010
    Inventors: Cheng-Chung Wang, Kenneth Wang
  • Patent number: 7742312
    Abstract: An electronic device and method of fabrication are provided. The electronic device comprises a substrate, a patterned conductive layer serving as an antenna layer formed on the outer surface of the substrate, electrically connected with a printed circuit board (PCB) for sending or receiving a wireless signal, wherein the substrate is placed between the patterned conductive layer and PCB. The patterned conductive layer may be electrically connected to the PCB through a hole in the substrate by a connecting piece. The substrate may be a housing of the electronic device.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: June 22, 2010
    Assignee: Lite-On Technology Corporation
    Inventor: Te-Wei Li
  • Patent number: 7737674
    Abstract: A voltage regulator. A pass element has a control gate and outputs an output voltage according to an input voltage and a control signal received from the control gate. A feedback circuit generates a feedback signal according to the output voltage. A bandgap circuit generates a reference voltage according to the output voltage. An amplifier generates a first signal according to the feedback signal and the reference voltage. A start-up circuit generates the control signal according to the reference voltage and the first signal.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: June 15, 2010
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Rogelio L. Erbito, Jr.
  • Patent number: 7736483
    Abstract: A method for electroplating low-resistance metal wire for resolving the problem to fabricate the metal wire on large-area substrate through the technology of photolithographing and etching in the prior art. Then the invention improves the RC-delay characteristic of circuit on large-area substrate and reduces the number of masks for processing of a structure of gate overlap lightly-doped drain (source) (GOLDD).
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: June 15, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Yau Huang, Cheng-Chung Chen, Yong-Fu Wu, Cheng-Hung Tsai, Chwan-Gwo Chyau, Fang-Tsun Chu
  • Patent number: 7736194
    Abstract: A universal electrical plug includes a first support, a second support, outer electrode slats, and inner electrode slats. An axis is defined from the second support to the first support. The outer and inner electrode slats are arranged on the second support, surround the axis, and extend to the first support in a direction parallel to the axis. The outer electrode slats are arranged on the second support and surround the inner electrode slats. Each outer electrode salt includes an outer deforming section bulged from the axis to fit insert holes of the electrical sockets with different sizes. Each inner electrode slate includes an inner deforming section depressed toward the axis to fit the electrode cores of the electrical sockets with different sizes. Through the outer and the inner electrode slats, the universal electrical plug is able to be adapted to the electrical sockets with different geometry specifications.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: June 15, 2010
    Assignee: Getac Technology Corporation
    Inventor: Pao-Hsing Chang
  • Patent number: 7735098
    Abstract: A method for executing computer programs in accordance with a preset priority is provided. The method is applicable to a computer system connecting to a data storage, a plurality of device selection buttons, and a plurality of multimedia players. The data storage is installed with a plurality of device drivers, a plurality of device application programs, and a program execution priority table. The program execution priority table defines correspondence between the device selection buttons and the multimedia players, and the priority order of execution of the device drivers and the device application programs of the multimedia players. When the computer detects any device selection button is pressed, the computer executes the device drivers and the device application programs corresponding the multimedia player in the priority order defined by the program execution priority table.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: June 8, 2010
    Assignee: Getac Technology Corporation
    Inventor: Yu-Chia Chang
  • Patent number: 7727370
    Abstract: A reference pH sensor, the preparation and application thereof. The reference pH sensor is an extended gate field effect transistor (EGFET) structure and comprises a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, a sensing unit comprising a substrate, a solid-state conductive sensing layer on the substrate, and a polypyrrole layer on the solid-state conductive sensing layer, and a metal wire connecting the MOSFET and the sensing unit.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: June 1, 2010
    Assignee: National Yunlin University of Science and Technology
    Inventors: Jung-Chuan Chou, Diing-Jia Tzeng
  • Patent number: 7728705
    Abstract: An electromagnetic transmission device. A guide bar connects to a fixed base and includes magnetic-permeable material and a first central height plane. A coil connects to the fixed base. A support base movably fits on the guide bar. An annular magnetic member connects to the support base and is surrounded by the coil. A magnetization direction of the annular magnetic member is perpendicular to a moving direction of the support base and annular magnetic member. The annular magnetic member includes a second central height plane. The coil interacts with the annular magnetic member to generate a first force. When moving to separate the second central height plane from the first central height plane, the annular magnetic member interacts with the guide bar to generate a second force, driving the support base and annular magnetic member to move along a direction perpendicular to the magnetization direction of the annular magnetic member.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: June 1, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Hsing Wang, Meng-Che Tsai, Yu-Hsiu Chang, Ji-Bin Horng