Abstract: A method for transferring control between hierarchically related cooperating sequential processes P and Q executable in a multi-processing CPU environment. The method uses pointers to identify active and suspended processes. The method steps comprise generating and memory storing activation records; transferring control from process P to process Q, and updating the process pointers to record the suspension of process P and the activation of process Q; and resuming execution in the most recently executing subprocesses of Q by reference to the process pointers.There is stored in memory one activation record per process. The record includes a pointer to the activation that is the parent of the process, a pointer to the most recently executing subprocess of the process, and information defining the current execution state of the process. These pointers are further constrained such that the set of activation records form the nodes of a tree whose arcs are defined by the parent pointers.

Abstract: Graphical data on a document is raster scanned and the resulting bit pattern is processed to provide a processed bit pattern which represents lines which each are a single pel in width and indicative of the shapes of objects scanned on the document. These single pel wide lines may represent the outlines of objects on the center lines. The processed bit pattern is then directed to a line follower in which bits representing contiguous pels are detected and tested for linearity. When contiguous pels fail the linearity test, a new vector is started and the vector being tracked is terminated. Hardware for performing these operations is described. The resulting vector list is stored until needed for display. Optionally a display station can be used to correct faulty vectors or to encode alphanumeric data in a more convenient format than vector coding.

Abstract: A demand access broadcast transmission method and means is capable of supporting random port access and any-to-any transmission at very high data rates. A communication medium (FIG. 2) formed from an inverted tree network of nodes (1, 18, 22) and full duplex connecting links (13, 17, 19) permits the establishment of a path lock up-link through the network from a demanding port to a root node on a first-come first-serve demand access basis with arbitration at each distinct tree node level (FIG. 3). Broadcast transmission is perfected down-link over all fan-out paths from the root node. Collision is avoided by locking a path to a port and by limiting race conditions among active ports to only the leading edges of messages. Thus, relinquishment of a broadcast channel overlapped with transmission of a message does not result in path seizure since the occurrence of message leading edges is the singular path connection invoking event.

Abstract: An apparatus for ensuring continuous flow through a pipeline processor as it relates to the serial decoding of FIFO Rissanen/Langdon arithmetic string code of binary sources. The pipeline decoder includes a processor (11, 23) and a finite state machine (21, FSM) in interactive signal relation. The processor generates output binary source signals (18), status signals (WASMPS, 31) and K component/K candidate next integer-valued control parameters (L0, k0; L1, k1; 25). These signals and parameters are generated in response to the concurrent application of one bit from successive arithmetic code bits, a K component present integer-value control parameter (52) and K component vector representation (T, TA) of the present internal state (51) of the associated finite state machine (FSM). The FSM makes a K-way selection from K candidate next internal states and K candidate next control parameters. This selection uses no more than K.sup.2 +K computations.

Abstract: Apparatus and method for enabling asynchronous, collision-free communication between ports on a local shared bus network which is efficient in the use of bus bandwidth and which, in one embodiment, provides a bounded, guaranteed time to transmission for each port.

Abstract: Data manipulation apparatus is described for converting raster-scanned data received, for example, from a scanner 2 at a first picture element (pel) resolution to a second lower pel resolution for display, for example, on a CRT terminal 4. The apparatus includes a scale-changing means 8 which functions to replace selected subgroups of pels in the input image by single pels at its output. The significance of each single pel reflects the presence or absence of a pel representing part of an image object in the associated subgroup of pels. The number of pels in the selected subgroups are determined by the degree of compression required to convert to the lower pel resolution. Prior to scale change, the apparatus functions to modify the input data in order to minimize merging of adjacent image objects as a result of scale change and thereby improve the legibility of the output image at the lower resolution.

Abstract: A method and means of arithmetic coding of conditional binary sources permitting instantaneous decoding and minimizing the number of encoding operations per iteration. A single shift and subtract operation for each encoding cycle can be achieved if an integer valued parameter representative of a probability interval embracing each source symbol relative frequency is used for string encoding and control. If the symbol being encoded is the most probable, then nothing is added to the arithmetic code string. However, an internal variable is updated by replacing it with an augend amount. If the updated internal variable has a leading zero, then both it and the code string are shifted left by one position. If the symbol being encoded is the least probable, then a computed augend is added to the code string and the code string is shifted by an amount equal to the integer valued parameter.

Abstract: Scale-changing method and apparatus is described for converting raster-scanned data received for example from a scanner 2 at a first picture element (pel) resolution to a second lower pel resolution for display for example on a CRT terminal 4. The apparatus includes a scale-changing means 3 which operates on receipt of the image data from the scanner 2 to perform a scale-change operation on the pels, first in the image row direction and then in the image column direction. The row scale-change operation is performed by scale-change projector 5 which functions to replace sub-groups of pels in the input image rows by single pels at its output. The number of pels in the sub-groups are determined by the degree of compression required to convert to the lower pel resolution.

Abstract: In a method and apparatus for reconstructing Chinese characters such as in a printer system, each of the characters is divided into a pair of components at least one of which occurs in one or more other characters. The components which have a height equal to the height of a standard character cell are stored together with information as to the locations of the components across the width of the standard character cell for each character. The components may be stored in a compressed form, in which event the information as to their location forms a part of the compressed data. When a given character is to be reconstructed, the first component thereof is transferred to a buffer where it is temporarily stored at the proper location across the width of a standard character cell. Thereafter, the second component is transferred to a logic circuit together with the temporarily stored first component, and the two are logically OR'ed to form the complete character.

Abstract: A method and means for creating the display illusion of "roughness" or "texture" in color patterns suitable for an raster scanned display surface by assigning different color values to pels (picture elements) in adjacent positions and then replicating the patterns automatically using the recurrent and sequential accessing of a concordance table. The real color of each pel of a textured pattern is a joint function of a color number stored in a refresh buffer driving the display surface for any given display matrix array pel position and the value of a predetermined subset of address bits which describe that pel position. The use of preselected pel position address bits for regulating texture is shown as applied to video lookup tables and refresh buffers as a singlelevel control and additionally to two or more video lookup tables for achieving a pattern hierarchy.

Abstract: A method and means for path independent reservation and reconnection of devices to CPU's operating in a multi-CPU and shared device access system environment. The multi-CPU and shared device access system comprises a plurality of sets of fan out paths (channels), each set coupling a corresponding CPU as a source node; a plurality of input/output devices; and a plurality of control nodes (control units), each node including means for accessing the devices, for selectively intercepting the paths in order to complete a signal path connection to a single destination device. Each control node further includes means (FIG. 2, element 25') for storing a table of independent path sets of CPU's and reserved devices and means (FIGS.

Abstract: An apparatus for simultaneously correcting several channels in error is combined with a parallel multi channel data handling system. The apparatus encodes and records vertical parity checks in a first channel and encodes and records parity checks in a second and third channel or equivalent taken over the channels in respective predetermined positively and negatively sloped directions.Upon readback, syndromes from the parity checks and the recorded data are obtained. Correction signals from at least two syndromes intersecting the same error in a known channel in error are formed. The values of the syndromes diagonally intersecting each error in the known channel are continuously modified as the error is detected by inversion of the simple parity. Correction is attained by logically combining the correction signals with the original known channel in error data.

Abstract: A method and means for the recovery of non-logged data by a CPU/channel from a storage subsystem, which data would normally be overwritten upon the subsystem being RESET by the CPU/channels. A defaulting control unit simultaneously initiates a DISCONNECT IN sequence to its attaching channels and sets an appropriate status bit at a control unit/control unit communications interface. The channel responds to the DISCONNECT IN with a SELECTIVE RESET interface sequence which sequence is buffered by the defaulting control unit. Meanwhile, the companion functioning control unit, when operating at its lowest interrupt level, polls the status bit periodically and offloads data registers through the interface connection from the defaulting unit within a predetermined time. At the end of this interval, the SELECTIVE RESET is honored, thereby erasing all data in the defaulting control unit registers.

Abstract: Where data is recorded on logically independent sets of parallel channels or tracks, the correction of error of very long (infinite) length cannot be advantageously treated by conventional coding methods unlike finite length error such as single shot or burst noise. To ensure the correction of channels in error from data recovered from a multi-channel storage medium, a fixed number of channels per set are dedicated to error checking bits. In this invention, more than the usual number of channels in error in any one set are made correctable by adaptively reallocating the unused redundant channels in the other set. This is accomplished by encoding and recording in the first redundant channel in each set vertical parity checks limited to that set while encoding and recording in the second redundant channel of each set, the parity of data taken over both sets of channels in a predetermined positively or negatively sloped direction.

Abstract: In a data processing system in which two or more asynchronous processors operating as masters interchange requests and responses with a control unit that in turn controls a number of peripheral devices and operates as a slave to the processors, repetitive requests from a high speed processor can give rise to an impasse condition in which the control unit is blocked from completing the previously initiated sequence between a peripheral device and another processor. In accordance with the invention, the interface between the processors and the peripheral devices incorporates means which detect an uninterrupted sequence, of predetermined length, of busy responses from the control unit. If such responses are not interrupted by other actions, the system temporarily exercises independent control, returning a busy signal to the processors while enabling the control unit to ascertain whether reconnection to a specific processor is needed as the next step in a previously initiated processor program.

Abstract: The wait relations among N tasks in a multiprocessing, multiprogramming CPU environment are conformed to a vector of N+1 fields recording which tasks in a system are active and upon what other task any given task directly waits. The vector may be stored in a global register. Positions 1 through N are assigned to the N tasks such that a value p in position r means that task r is waiting directly on task p. One value j of the possible values 0,1,2, . . . , N+1 is designated to indicate an active task. Position j always shows the value j. Without loss of generality and to facilitate the discussion j is assumed to be 0. Thus, the value 0 in register position r means that task r is not waiting and position 0 always has the value 0.The presence of any deadlocks (closures) among the wait relations can always be detected by the computing system by making repeated translations of the vector fields within and upon themselves in no more than log.sub.2 (N+1) iterations. In this regard, log.sub.

Abstract: Method and means are described for the tracking of digit significance upon operands arithmetically combined in a series of binary operations such as addition, subtraction, or shifting in a decimal computer. The digits are decimally encoded in a format having enough excess capacity such that nonsignificant digits are unique. As part of the arithmetic combining of the operand, pairs of digits of like order but possibly mismatched as to significance and by observing a predetermined rounding rule may also cause a carry value to be propagated to a digit position of higher order. In subtraction by complement addition, an additional carry is propagated to a higher order position conditioned upon there being either a local overflow, a nonsignificant subtrahend, or a nonsignificant minuend and a subtrahend less than an amount specified by a rounding rule. Between the two operands, this results in the rounding of the more precise operand to the least significant digit position of the less precise operand.

Abstract: A loop system couples a CPU channel to bulk storage devices via a loop controller and device adapter. The loop system is characterized by equal fixed-length, multi-byte frames, each frame of which being assignable to only one terminal at a time. The system is further characterized by having a fixed loop delay greatly exceeding the frame duration by virtue of the high data rate.Dynamically variable frame assignment occurs when the primary terminal generates an unassigned empty frame in response to each assigned full (read) frame from a secondary terminal. The primary further generates an assigned full (write) frame upon receipt of each service (write) request frame from a secondary terminal. Lastly, the primary can send access command frames for each received unassigned empty frame or any other frame that does not imply a demand for bandwidth by the secondary.

Abstract: Systematic and noise-induced errors, as detected in words extracted from corresponding locations in a m .times. n word organized memory array, are distinguished as to their source and are corrected by using the conjunction of a nonzero error checking syndrome and the a'priori location defects status as indexed by the location address of the extracted words from an external table memory.

Abstract: In an apparatus for generating variable length codewords c(a.sub.i) and c(a.sub.j) responsive to corresponding fixed length codewords b(a.sub.i) and b(a.sub.j), where a.sub.i and a.sub.j are source alphabet characters, a.sub.i .epsilon. A.sub.1 and a.sub.j .epsilon. A.sub.2, ambiguity arises whenever any fixed length character to be encoded can instantaneously represent source characters a.sub.i and a.sub.j drawn from two or more dissimilar alphabets i.e. A.sub.1 or A.sub.2. This is resolved by the inclusion of a Markov processor in combination with the apparatus. The processor establishes the point in the sequence when transitions occur between fixed length characters in one alphabet to fixed length characters in another alphabet by the message context. The processor includes a map of state and transition paths.