Abstract: An improvement in a phase locked loop comprising a VCO for generating a signal S.sub.VCO of frequency f.sub.VCO, a divider for dividing f.sub.VCO to produce a signal S.sub.N of frequency f.sub.N, a reference signal generator for generating a reference signal S.sub.R of frequency f.sub.R, and with said VCO responsive to a particular value E.sub.c of a variable control signal e.sub.c to cause f.sub.N =f.sub.R for a given value of N, the improvement consisting of a phase/frequency detector for detecting and correcting frequency and phase differences between S.sub.N and S.sub.R to cause f.sub.N =f.sub.R and comprising a three stage left/right shift register responsive to one of signals S.sub.N or S.sub.R to shift binary O's into the first stage thereof in the right direction and responsive to the other of signals S.sub.N or S.sub.R to shift binary 1's into the third stage thereof in the left direction.

Abstract: A length of conventional hollow waveguide having an interior rectangular cavity has openings in the broad walls along a common axis. A diode support structure positions a negative resistance diode in the waveguide through one opening. A DC bias conductor structure positions a bias conductor through the other opening and into contact with the diode to provide a DC bias thereto. These two structures are secured together and to the conventional waveguide structure.

Abstract: A decoder for reconstructing a standard composite video signal with standard synchronizing pulses from a video signal V with only gray sync encoding E.sub.GS, of a repetition rate f.sub.GS, and comprising a first generator for generating a signal E.sub.VCO having a controllable frequency f.sub.VCO which, in the absence of frequency control, is slightly different from f.sub.GS, a second generator responsive to E.sub.VCO to form a composite blanking signal E.sub.B having a repetition rate equal to f.sub.VCO so that E.sub.B will slew with respect to E.sub.GS until E.sub.B and E.sub.GS become synchronized and a summer for summing E.sub.B and V to produce a reconstructed standard composite video signal when E.sub.B and E.sub.GS become synchronized. There is further provided a phase lock circuit for phase locking E.sub.VCO with the standard synchronizing pulses of said reconstructed video signal to maintain E.sub.B and E.sub.GS in a synchronized relationship.

Abstract: A data processor system having a total memory capacity, an integrated circuit chip having thereon a central processing unit (CPU), a ROM, a RAM, a first decoder responsive to addresses supplied thereto for determining the location of the RAM in the total memory capacity, and logic for disabling the ROM from the CPU and for relocating the RAM in the total memory capacity. Also provided are a generator for generating a first control signal having first and second states, first gating logic responsive to the first state of the control signal to disable the ROM and to disconnect the output of the first decoder from the RAM.

Abstract: A velocity control system for a rotating disc having a spiralling track thereon and comprising an arm rotatable about a fixed axis, a stylus attached to such arm and positioned to follow the spiralling track, and logic responsive to the position of the arm to produce a control signal indicative of the position of the arm. Also provided is a prime mover responsive to the control signal to rotate the disc at an angular velocity to produce a velocity at the point of contact between the stylus and the disc which is a predetermined function of the position of the stylus.

Abstract: In a data processing system having a memory and employing N-bit bytes and two byte addresses, a branch instruction which can cross one page boundary is executed without having to use calculations to effect a change in the contents of the program counter (PC). It is determined whether the value V1 of the (N-1) least significant bits (LSB's ) of the lower order byte of the two byte branch address is greater or less than the value V2 of the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing and also whether PC N.noteq.BR N where PC N and BR N are the most significant bits of the lower order bytes of the PC address and the branch address, respectively. If V1<V2, PC N=1, and PC N.noteq.BR N, the upper order byte of the PC address is incremented by 1 and if V1>V2, PC N=0, and PC N.noteq.BR 7, the upper order byte of the PC address is decremented by 1.

Abstract: A phase locked-loop circuit includes a non-linear voltage controlled oscillator ideally producing a desired output frequency as a function of time and a memory producing signals which add to the phase locked-loop phase error feedback signal to correct for the VCO non-linearities. A calibration circuit upon activation is responsive to the phase error feedback signal for altering the contents of the memory such as to reduce or eliminate the phase error.

Abstract: A plurality of FET or other amplifiers are connected between respective outputs of an N output port power divider network and respective inputs of an N input power combining network in a variable power amplifier system. A gate bias is selectively supplied to each of the amplifiers which is either at a first value to cause the amplifier to amplify or at a second value to cause the amplifier to be cut off and therefore to not dissipate any DC power. The number of amplifiers receiving the first potential is determinative of the amount of power amplification of the variable power amplifier.

Abstract: A sensor for measuring motion past the sensor of a non-magnetic conductive part surrounded by a non-magnetic conductive shield. The sensor consists of a bias magnet and pickup coil located outside the shield. Eddy currents are generated in the part as it moves through the magnetic field of the bias magnet. The eddy currents create an electromagnetic field around the part that penetrates the conductive shield causing the generation of secondary eddy currents in the shield. Secondary electromagnetic fields created by the secondary eddy currents induce a voltage in the pickup coil, a parameter of which is indicative of motion of the part.

Abstract: A circuit coupled between an indicating pushbutton panel switch and a software-programmable processor permits program control over the effect of switch actuation and over the illumination of the indicators. The processor can disable the switch function, blanking the indicators; it can accept a manual actuation of the switch, changing the illumination; it can reject as invalid a switch actuation within a multiple-switch field, retaining the current illumination; and it can alter the illumination in the absence of switch actuation. In one embodiment the signals providing the switch and indicator status are channeled into a serial data stream and transferred to the processor input register.

Abstract: A frequency-modulated continuous-wave (FM-CW) ranging system produces a first signal of frequency corresponding to the measured range of a target which signal is sometimes below a given quality and produces a second signal of frequency corresponding to the measured range of a simulated target of known range. A threshold detector determines when the target signal is above the given quality at which time the period of the first signal is determined from a given cycle thereof while concurrently the period of the second signal is determined from which the range to the target can be computed.

Abstract: A signal processing system for use with a radar ranging system which transmits a radio frequency beam of finite angle to a sloping target of not greater than some known slope and creates from the return signal a beat frequency signal comprising various frequencies corresponding to the various distances from the ranging system to the target. The processing system includes a first tracking bandpass filter which is caused to seek and lock onto the lowest frequency F.sub.L in the beat frequency signal. Given frequency F.sub.L, the angle of the beam and the maximum slope of the target, a theoretical maximum frequency F.sub.X is computed. A second tracking bandpass filter tracks down from frequency F.sub.X to and locks onto frequency F.sub.H, the frequency component in the beat frequency signal associated with the maximum range to the target. From frequencies F.sub.L and F.sub.H and the beam angle, the average range to and/or slope of the target can be computed.

Abstract: A tracking filter system including a phase locked loop and a tracking filter is receptive of an input signal of frequency A and undesired frequency X from a signal source such as a frequency modulated/continuous wave radar range measuring system. The phase locked loop circuit receives the input signal and produces a control signal corresponding to a frequency intermediate frequencies A and X. The tracking filter is set by the control signal to pass frequencies above or below the intermediate frequency and thus to pass frequency A and to reject frequency X.

Abstract: A tri-state logic circuit which, upon failure of its operating potential, produces a high impedance between its output terminals. The tri-state logic circuit includes first and second complementary conductivity type transistors each with a control electrode and with a conduction path. The paths are connected in series to the operating potential. The control electrode of the first transistor is connected to an intermediate point in a series switching circuit the ends of which are connected to the operating potential. The series circuit is responsive to the presence of the operating potential and to binary data and control signal inputs of given values for causing the conduction path of the first transistor to assume a low impedance state. The series circuit also includes on both sides of said intermediate point devices responsive to a loss in the operating potential for causing the first transistor to assume a high impedance state irrespective of the value of the data and control signals.

Abstract: An FM transmitter linearity test equipment includes an amplitude modulation generator signal source producing an amplitude modulated signal of known varying amplitudes changing at a known rate and a demodulator for demodulating the resulting frequency FM signal from the transmitter. The test equipment also includes a commutating filter operating at said known rate and which is receptive of the demodulated signal for producing a signal of varying amplitude which is compared with the signal produced by the signal source to determine the linearity of the FM transmitter.

Abstract: A frequency synthesizer of the phase-locked loop type, having an output circuit circuit which produces an output signal at any of a plurality of alternating frequency values depending on the value of a command signal applied to the output circuit. The synthesizer includes a storage apparatus for storing, for each frequency value, an indication of the precise command signal value which causes the frequency to be produced.

Abstract: An amplifier including an in phase feedback signal to therefore exhibit negative resistance is receptive of an input alternating signal which includes a frequency F. The output of the amplifier is coupled to a resonator adjusted to a center frequency F and having undesirable resistance which is offset by the negative resistance of the amplifier. The resonator includes an inductor and adjustable capacitor arranged either in series or in parallel with the amplifier to therefore change the value of F.

Abstract: An attitude control system for spacecraft having thrusters utilizes the exhaust plume of the thrusters for attitude control. At least one of the thrusters is canted so that its reaction line of thrust, when misaligned with one of the spacecraft's primary axes; causes a control torque to develop about said axis which aids the plume torque about said axis resulting from the plume of the one thruster impinging on a surface such as that of a solar panel on the spacecraft.

Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter. Improved memory addressing means facilitates altering the spark advance in accordance with a sensed condition such as manifold vacuum, and conserves memory space.

Abstract: A pseudo random number generator for generating a succession of numbers manifesting solely three values at random from two-bits.