Abstract: Improved data acquisition systems and methods that enable large numbers of data samples to be accumulated rapidly with low noise are described. In accordance with this inventive approach, a plurality of data samples is produced from a transient sequence in response to sampling clock, and corresponding data samples across the transient sequence are accumulated in response to an accumulation clock that is shifted in phase relative to the sampling clock.

Abstract: A method for forming a crater-style sampling capacitor. The capacitor includes a dielectric having a smooth crater shaped input electrode on a first surface and output and guard electrodes on a second surface. A sampling capacitor is defined by the input and output electrodes, and a guard capacitor is defined by the input and guard electrodes. The edge of input electrode is positioned below the first surface to increase surface flash over voltage, further, the input electrode is curved to eliminate corona discharge at edges of the input electrode and to reduce self-heating to negligible levels. The apparatus is suitable for high-voltage radio-frequency applications, such as a mass spectrometer, or other high-voltage applications that require an accurate sampling capacitor for amplitude control and accurate sampling of radio-frequency wave-forms.

Abstract: A high-strength solder interconnect formed on a copper/electroless nickel/immersion gold metallization solder pad and method. The invention provides a low cost, high-strength solder interconnect on a copper/electroless nickel/immersion gold metallization (CENIGM) pad that can be formed at a temperature at or below the temperature used in eutectic tin-lead (Sn—Pb) solder applications. The invention includes a first substrate having a solder-wettable pad and a second substrate having a copper/electroless nickel/immersion gold metallization (CENIGM) solder pad. The invention also provides a solder interconnect between the solder-wettable pad and the CENIGM solder pad. The invention may provide a solder interconnect that includes a solder body including at least 2% indium (In) by weight and wetted to both the CENIGM solder pad and the solder-wettable pad.

Abstract: A surface mountable coaxial solder interconnect. The invention provides a small, low-cost, passively self-aligning, high-frequency electronic interconnect adapted to mass production and method. The invention includes a substrate, a signal conductor, and an annular conductor. The substrate incorporates an annular pad and a signal pad substantially centered within the annular pad. The signal conductor includes reflowed solder and is wetted to the signal pad. Similarly, the annular conductor includes reflowed solder and is wetted to the annular pad. The invention may also provide a second substrate substantially parallel to the first substrate that includes a second annular pad and a second signal pad substantially centered within the second annular pad. In such a case, the signal conductor is also wetted to the second signal pad, and, similarly, the annular conductor is also wetted to the second annular pad. The method of the invention includes obtaining a mask and a substrate.

Abstract: A mixed solder paste that reflows below 158° C., and, once reflowed, forms a solder alloy with a melting temperature at least 10° C. higher than the reflow temperature of the mixed solder paste, without ternary eutectic structures occurring at approximately 96° C., and with a uniform microstructure. The mixed solder paste according to the invention includes an eutectic or near eutectic tin-lead (Sn—Pb) solder powder, an eutectic or near eutectic lead-bismuth (Pb—Bi) solder powder, and a flux vehicle. The Sn—Pb solder powder and the Pb—Bi solder powder are mixed in a ratio between about 51:49 and about 77:23, but preferably between 55:45 and 65:35. These ratio result in a solder alloy with a mass consisting of 14% and about 25% Bi and between about 35% and about 45% Pb. The invention further provides a method for forming a mixed solder paste for low temperature soldering.

Abstract: A ferroelectric liquid crystal-based switchable half-wave plate with improved alignment control, a ferroelectric liquid crystal-based light valve system with improved contrast control, and a method of improving contrast in a ferroelectric liquid crystal-based light valve system. The switchable half-wave plate with improved alignment control includes a layer of ferroelectric liquid crystal material sandwiched between a first transparent electrode and a second transparent electrode. The switchable half-wave plate also includes an electric field direction switching circuit configured to switch the electric field across the liquid crystal material between the forward direction and the reverse direction in response to a control signal. The switchable half-wave plate additionally includes an electric field magnitude control circuit to adjust the tilt angle in response to a signal received at a alignment control signal input.

Abstract: A method of automatically generating a software installation package. The method operates on an application program that has been ported to and debugged on a target computer system. A manifest is automatically generated, listing all application program files that must be installed on the target computer system. Then the method automatically determines which resources, in particular shared libraries, are needed by any of the listed files. Necessary filesets and subproducts are then automatically generated. Program files are then automatically assigned to the filesets and filesets are automatically assigned to the subproducts. The need for control scripts is automatically detected and control scripts are automatically generated. Then the installation package is generated by combining the listed files, filesets, subproducts, control scripts, the needed resources, and any related installation materials.

Abstract: A computer program which causes a computer to correct a uniform resource identifier (URI) in a noisy source document. The program finds and corrects potential errors within a URI before turning the URI into a hyperlink. Testing the corrected URI is done by seeking the resource described by the corrected URI. Testing the URI also includes parsing the URI, identifying potential syntax errors within each portion of the URI, creating alternative URI combinations, and prioritizing the alternative URI combinations. Syntax errors corrected include incorrect protocol, incorrect or missing component separator characters, incorrect spacing, incorrect or missing dot character, and alphanumeric character replacement.

Abstract: A printed circuit board for minimizing thermally-induced mechanical damage of solder joints electrically connecting electronic components to the printed circuit board. The printed circuit board includes a first substrate, solder pads, and an expansion layer. The first substrate has two substantially parallel major surfaces, and a first coefficient of thermal expansion (CTE). The solder pads are located on one of the major surfaces of the substrate. The expansion layer has a second CTE, different than the first CTE, and is affixed to a portion of one of the major surfaces. The expansion layer is also arranged to provide a predetermined degree of bending for a given temperature change to a portion of the first substrate proximate to the expansion layer and to two of the solder pads, thus forming a concavity in the portion of the substrate.

Abstract: An articulated nose bridge for a head mounted display for adjusting the height, tilt, and distance of the display on the wearer's face. The articulated nose bridge including a nose piece configured to rest on a wearer's nose, a bridge piece located between a left eye display and a right eye display of the head mounted display, and an articulator. The articulator includes a nose end coupled to the nose piece, and a bridge end pivotally coupled to the bridge piece and allowing a viewing angle of the left eye display and the right eye display to be adjusted by the wearer. The articulated nose bridge may additionally include a locking mechanism having a locked position that prevents the bridge end of the articulator from pivoting and a free position that allows the bridge end of the articulator to pivot. The locking mechanism may include a spring or tensioner that automatically returns the locking mechanism to the locked position after the wearer has moved the locking mechanism into the free position.

Abstract: An micro-photonics module includes an optical component and a photonics device mounted on a single substrate. The substrate defines a rectilinear cavity with flat bottom and flat side. The photonics device mounted on the substrate at a predefined distance from the cavity defines an optical path aligned to cross the rectilinear cavity. The optical component with portion abutting the flat bottom, flat side, and locator surface, is aligned with the optical path by the flat bottom and flat side of rectilinear cavity. The substrate may also define pyramidal cavity formed into the substrate from a major surface of the substrate, a notch formed in the substrate from the major surface and the flat side of the rectilinear cavity, and a locator surface within the rectilinear cavity. A ball lens may be seated in contact with the substrate within the pyramidal cavity to have a predefined relationship with the photonics device. The notch allows light to pass unobstructed between the ball lens and the optical component.

Abstract: A structure having substantial surface evenness is created by a method in which an insulating layer (24) that has an upward protrusion (26) is formed on a patterned conductive layer (20) having a corresponding upward protrusion (22). A further layer (28) having a generally planar surface is formed on the insulating layer. Using an etchant that attacks the further layer much more than the insulating layer, the further layer is etched to expose at least part of the insulating protrusion. The further layer and the insulating layer (as it becomes exposed) are then etched with an etchant that attacks both of them at rates not substantially different from each other. This brings the upper surface down without exposing the conductive layer, particularly its upward protrusion.

Abstract: An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.

Abstract: A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V.sub.IN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V.sub.OUT) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: A multi-stage amplifier (21, 22, 23, or 24) has three or more amplifier stages (A1, A2, and A3) arranged in a capacitatively nested configuration for frequency compensation. The technique consists of nesting two of the stages together with a pole-splitting capacitor (C1) to form a stable device (21 or 22) and then nesting this device and a third of the stages together with another pole-splitting capacitor (C2) to form the amplifier.

Abstract: A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representative signal amplification across the supply range, although neither differential portion individually does so. A current control (24) regulates operating currents (I.sub.N and I.sub.p) for the differential portions in such a way that the amplifier transconductance can be controlled in a desired manner as the common-mode part (V.sub.CM) of the amplifier input signal (V.sub.I+ and V.sub.I-) varies across the supply range. The transconductance is typically controlled to be largely constant. A summing circuit (26) selectively combines internal currents (I.sub.A, I.sub.B, I.sub.C, and I.sub.D) from the differential portions to generate at least one output signal (I.sub.O+ and I.sub.O-) representative of the input signal.

Abstract: A layer of a conductive material consisting of aluminum alone or in combination with a small percentage of copper and/or silicon is formed on a semiconductor surface in a two-step deposition process in such a manner as to largely avoid serious continuity defects in the layer.

Abstract: A bipolar voltage translator contains a pair of differentially coupled transistors (Q1 and Q2) for converting an input voltage (V.sub.IN) supplied to one (Q1) of the pair into an output voltage (V.sub.OUT) taken between the other (Q2) and a first resistor (R9). A further transistor (Q4) coupled through a second resistor (R12) to a V.sub.EE supply provides current for the differential pair. A voltage reference circuit (10) containing at least three serially coupled diodes (S5, J3, and J4) with a resistive voltage divider (R13 and R14) across an intermediate one (J3) of the diodes provides the current-source transistor with a reference voltage (V.sub.REF2) that equals V.sub.EE +(1+.alpha.)V.sub.BE where .alpha. is 0.2-3.0. The ratio of the first resistor to the second is desirably .beta./.alpha. where .beta.is the output voltage swing divided by V.sub.BE. If .beta. is 1 and the transistors are NPN devices, the output voltage level is suitable for current tree logic.