Patents Represented by Attorney R. Mayer
  • Patent number: 4461963
    Abstract: A MOS power-on reset circuit includes Schmitt trigger circuit and an inverter. The Schmitt trigger circuit comprises first, second, and third depletion transistors serially connected between reference potential and supply voltage. The first and second depletion transistors are connected at a first junction point, and the second and third depletion transistors are connected at a second junction point. The gates of the first and second depletion transistors are commonly connected for receiving an input substrate bias voltage. An enhancement transistor is connected between the first junction point and supply voltage. The gates of the enhancement transistor and the third depletion transistor are commonly connected to the second junction point, which is the output of the Schmitt trigger circuit and which is coupled to the inverter from which the output voltage is taken.
    Type: Grant
    Filed: January 11, 1982
    Date of Patent: July 24, 1984
    Assignee: Signetics Corporation
    Inventor: Joannes J. M. Koomen
  • Patent number: 4439692
    Abstract: A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.
    Type: Grant
    Filed: December 7, 1981
    Date of Patent: March 27, 1984
    Assignee: Signetics Corporation
    Inventors: Jan J. P. M. Beekmans, John B. Hughes
  • Patent number: 4398105
    Abstract: An arbiter circuit includes a latch made of two crosscoupled NAND gates, one of which is a Schmitt NAND gate, a difference detector, and two output NOR gates. The output of the latch is coupled to the difference detector and to one input of the NOR gates. The NOR gates receive another input from the difference detector. The difference detector is responsive to a voltage difference that exceeds one V.sub.BE, thereby blocking signals that originate in the latch during oscillating or metastable states of the latch, which may include rut pulses.
    Type: Grant
    Filed: January 22, 1981
    Date of Patent: August 9, 1983
    Assignee: Signetics Corporation
    Inventor: Philip J. Keller