Abstract: A method of chemically vapor-depositing a low-stress glass layer onto a substrate which is heated in an atmosphere including silane, oxygen, and an inert carrier gas, comprises the step of adding water vapor to the atmosphere to increase the water vapor content of the atmosphere substantially above that normally present therein from the oxidation of the silane.

Abstract: A semiconductor structure from which various types of active semiconductor devices can be formed is made of a semiconductor island on a transparent substrate, having thereon an electrically insulating layer of a protective material, such as silicon dioxide, which extends onto and covers the sides of the semiconductor island. The protective layer can either cover only the sides of the semiconductor island or extend over the top edge of the island. The protective layer is made by etching through a photoresist mask made of a negatively reacting photoresist which is formed by exposure to irradiation from beneath the uncovered surface of the substrate, whereby the thickness of the silicon island and the flux density of the irradiation are selected so that for a particular duration, the irradiation is completely attenuated by the semiconductor island.

Abstract: The device includes an alignment station at which an operator can align a wafer under a microscope. Once the wafer is properly aligned, a transfer chuck is brought into position above the wafer and aligned with alignment pins located in fixed positions at the alignment station. The wafer is then fixed to the transfer chuck and released from the alignment station. The transfer chuck is moved into proper alignment with alignment pins at a remote operation station, such as an automatic scribing station. The invention allows the operator to view the wafer with semiconductor devices facing the operator and provides for flipping the wafer over through the use of the transfer chuck so that the laser scriber can scribe the wafer on the side away from the semiconductor devices.

Abstract: A pyrogenic oxide is grown on a silicon wafer in a furnace by oxidizing hydrogen in the presence of an excess amount of oxygen as well as anhydrous hydrogen chloride to produce steam within the furnace. After growing a suitable pyrogenic oxide layer, the hydrogen and hydrogen chloride flows are turned off while the oxygen flow is continued to grow a dry oxide. A nitrogen anneal while the wafer is slowly pulled from the furnace completes the hybrid, radiation hard oxide layer.

Abstract: The source and drain of an N-MOSFET can be brought closer together without substantially increasing capacitance and punch-through effects, by using a very high resistivity P-substrate, a moderately high resistivity P- type region in the channel zone and a thin but low resistivity surface-adjacent channel portion through which current flows. The P- type region and the surface-adjacent channel portion are ion-implantations. The P- type region extends deep enough into the substrate to shield the source from electrostatic coupling with the drain. Diffused, low reactance integrated circuit resistors can be made using the same principles.

Abstract: A plurality of Schottky barrier devices are produced by a method which uses a relationship between barrier height, surface concentration of impurities, and alloying time valid when a thin layer of oxide is present on a device substrate and includes the steps of preselecting an impurity concentration for the principal surface of a plurality of silicon substrates and using a predetermined alloying time for each substrate to achieve a preselected barrier height.

Abstract: An insulated gate field effect transistor having spaced highly doped source and drain regions with less highly doped source and drain extensions, which define the ends of the channel of the transistor, has both the source and drain extensions and the channel of the transistor defined in a controllable manner by the steps of forming a continuous zone of the same conductivity type as the source and drain regions in the space between these two regions and then counterdoping a portion of this layer.

Abstract: Removal of selected, isolated defects comprised of excess chromium (Cr) or chromium oxide (Cr.sub.2 O.sub.3) from photomasks comprises contacting at least the defect area by a suitable acid and initiating the etch of the defect area by contacting the defect area with a metal probe made from a suitable material. Excess chromium or chromium oxide areas may be isolated by using a laser to separate the areas from areas which are to remain.

Abstract: A readout device is disclosed which comprises a substrate of semiconductive material having a source and drain region formed therein. These regions of the device are placed adjacent to the surface of a dielectric storage medium, selective portions of which, i.e. selective storage locations, are electrostatically charged. The dielectric storage medium has a layer of conductive material formed thereon to which a signal is applied in order to determine whether the storage location being accessed is charged, and, in one embodiment, to determine what the magnitude of that charge might be.

Abstract: A chuck for use in the testing of semiconductor wafers comprising first and second pluralities of electrically conductive members alternately arranged to provide a wafer receiving surface. The members are substantially completely electrically isolated from each other. Electric power leads and measurement sensing leads are provided to the first plurality of conductive members and the second plurality of conductive members respectively.

Abstract: The circuit protects the oxide of MOS devices from destructive breakdown by limiting the potential difference which can exist between two circuit nodes. By forming a protective circuit between each pair of nodes in the circuit, the range of voltages which can exist between any two nodes is predetermined, and the range can be fixed to prevent damage to the MOS devices. The protective circuit comprises a pair of diodes, a resistor, and a bipolar transistor.

Abstract: A method of fabricating a semiconductor device having a one type conductivity portion substantially surrounded by a second type conductivity portion is disclosed. The method involves selectively diffusing different impurities having the same conductivity inducing effect. The disclosed method is particularly adaptable to forming a plurality of devices in a relatively thick semiconductor wafer.

Abstract: A monolithic semiconductor device including a resistor comprising a first region of one type conductivity, has means for controllably establishing the value of the resistor comprising two additional regions of the opposite type conductivity disposed respectively on opposite sides of the conductive path of the resistor, whereby the width of the resistor is defined by the extent of the additional regions into the first region. Where the monolithic semiconductor device comprises an integrated circuit device including a lateral transistor, the additional regions may be formed simultaneously with the emitter and collector regions of the transistor while utilizing the same doping mask, whereby any variation in the base width of the transistor is made proportional to the variation in the width of the resistor.

Abstract: A semiconductor device including a body of semiconductor material with a metallic conductor disposed thereon has a combination glass/low-temperature-(typically 300.degree. C) deposited Si.sub.w N.sub.x H.sub.y O.sub.z passivating overcoat with improved crack and corrosion resistance. This nitride is formed over the conductor, with the glass over the nitride.

Abstract: A semiconductor device including a body of semiconductor material with a metallic conductor disposed thereon has a combination glass/low-temperature-(typically 300.degree. C) deposited Si.sub.w N.sub.x H.sub.y O.sub.z passivating overcoat with improved crack and corrosion resistance. A primary passivating layer including Si.sub.3 N.sub.4 is between the semiconductor surface and the metallic conductor, and the glass is formed over the metallic conductor, with the low-temperature-deposited nitride over the glass.

Abstract: A semiconductor wafer is cleansed of loose foreign surface matter and chemical impurities near the surface in an apparatus which passes superheated steam over the wafer. Condensate is permitted to form and drip off the wafer. After rising above 100.degree. C the wafer becomes dry, and is removed from the apparatus and then permitted to cool.

Abstract: A method is provided for the manufacture of a semi-planar silicon-on-sapphire composite comprising a sapphire substrate, an epitaxial monocrystalline silicon mesa formed adjacent the substrate and an epitaxial deposition of monocrystalline aluminum oxide surrounding the mesa. An essential step in the method is deposition of the aluminum oxide simultaneously adjacent the sapphire substrate and the monocrystalline silicon mesa whereby aluminum oxide formed adjacent the silicon mesa is polycrystalline and aluminum oxide deposited adjacent the sapphire substrate is monocrystalline. This enables the selective removal of the polycrystalline aluminum oxide adjacent the surface of the monocrystalline silicon mesa, thereby forming the composite.

Abstract: A method and apparatus for implanting dopant material into a substrate of semiconductive material in a preselected pattern without utilizing a mask comprises the use of a source template which is formed of the desired dopant material in the configuration of the pattern to be implanted. Ions of the dopant material are sputtered from the template by bombardment with an ionized gas, and these dopant ions are then filtered from unwanted ion species and accelerated into the substrate while remaining in the original template pattern.

Abstract: A resistive device for use as a current feedback loop in an integrated CMOS shift register circuit is made of an island of polycrystalline silicon with a sheet resistivity of from 10.sup.6 to 10.sup.8 ohms per square. The polycrystalline silicon island has two contacts thereon fashioned in the manner of MOS source and drain contacts and a dummy polycrystalline silicon insulated gate contact thereon. The device structure is designed to be and is fully compatible with CMOS mesa processing. The method for making the device incorporates into the processing steps for CMOS manufacture the formation of polycrystalline silicon islands on the substrate along with monocrystalline silicon islands. In the process, the polycrystalline silicon island is doped, through source and drain mask openings, with impurities of the same conductivity type as that predominating in the polycrystalline silicon island.

Abstract: An improved integrated transistor device has reverse bias breakdown protection for the base-collector junction. The base-collector junction is protected by means of a diode region providing a punchthrough protective mode of operation. The configuration disclosed provides a device which has comparatively stable and relatively high energy junctions therein.