Abstract: A silicon-gate insulated gate field effect transistor device has a thick field oxide in contiguous surrounding relation to its gate electrode and with a surface coplanar with or slightly higher than the surface of the gate electrode, thus facilitating crossovers and contacts to the gate electrode. The method of making this device includes forming a self-aligned silicon gate structure on a silicon wafer, masking the gate structure against the diffusion of oxygen, and thereafter oxidizing the silicon wafer to grow a thick silicon dioxide layer in surrounding relation to the silicon gate structure.

Abstract: A machine for separating a sheet of brittle material, for example a semiconductor wafer, into a plurality of pellets is disclosed. The pellets are defined by a plurality of intersecting scribed lines on the sheet. The machine includes a member for applying a shear force to an edge of the sheet whereby the maximum bending moment is applied at a preselected scribe line. The machine is particularly applicable for use with those semiconductor wafers which have a solder coating on both sides.

Abstract: The dryer is used for drying developed photomasks of the type used in manufacturing integrated circuit devices. The dryer provides a continuous flow of very clean, warm, dry air over photomasks placed in it to dry. The dryer comprises a box having a series of distributor tubes extending into it. Drying racks holding photomasks hang from the distributor tubes and heated, filtered air flows from at least one slot in the distributor tube over the wet photomasks to dry them.

Abstract: Semiconductor thyristor devices with means, inherent in the structure thereof, for protecting the devices against damage due to breakover. The means requires, in a semiconductor controlled rectifier device, for example, that the active gate region have a comparatively smaller total charge than the adjacent base layer separating the active gate region from the anode layer.

Abstract: A complementary integrated circuit device, adapted for fabrication with relatively high circuit density, includes relatively fast transistors with a closed gate geometry. Permanently-off gates surround transistors to isolate them from other transistors.

Abstract: An improved interconnecting line for an integrated circuit comprising a P+ silicon island having an optional first layer of silicon dioxide or a like material thereon and a second layer of silicon nitride or a like material adjacent the first layer, is provided. The line may be manufactured by improvements in the standard P channel MOS or MNOS processing method wherein the line is formed concomitantly with the island upon definition of the silicon. The line may be subsequently coated with silicon dioxide during formation of a gate oxide for a MNOS device and then coated with silicon nitride.

Abstract: A process for forming a blind hole having an isosceles trapezoidal cross-section in a sapphire substrate using a sulfur hexafluoride gas etchant and an etch mask of silicon nitride on top of silicon dioxide. A composite of sapphire, silicon dioxide and silicon nitride wherein silicon dioxide is located in between the sapphire and the silicon nitride; and the silicon nitride and silicon dioxide are congruently apertured.

Abstract: A silicon substrate is coated with a mask comprised of the combination of a silicon dioxide layer and a layer of undoped polycrystalline silicon. Aluminum is then diffused through windows formed in the mask. The mask has proven effective for relatively deep aluminum diffusion.

Abstract: The process employs both silicon dioxide and silicon nitride layers used for selectively masking areas to be etched in order to allow a single photomask to be used for defining areas having different conductivities simultaneously, thereby eliminating problems caused by misregistry between photomasks.

Abstract: A high voltage semiconductor device structure comprises a novel edge contour which directly contributes to increased voltage handling capability. Such a structure may further comprise a collector region shaped in coordination with the edge contour to provide a device having higher voltage capability.

Abstract: A method of making a semiconductor device which has regions of differing type and/or degree of conductivity includes the use of a multi-layer masking coating on selected regions of a body of semiconductor, and a mono-layer masking coating on other selected regions. Ion implantation together with chemical diffusion is used with a single photoresist mask to create regions of both relatively high and relatively low conductivity of one type. A second photoresist mask may be used with ion implantation and chemical diffusion to produce regions of opposite type conductivity with differing degrees of conductivity.

Abstract: A monolithic array of insulated gate field effect transistors useful, for example, as a read-only memory, has means for defining a pre-selected array of operative and non-operative transistors in a row and column arrangement. Non-operative transistors include diffused regions lying in the conductive channel zones thereof which serve to raise the value of the threshold voltage of these transistors above a value normally applied to the gate electrodes of all the transistors in the operation of the device. Operative transistors have no such threshold-raising diffused regions in their channel zones so that they can be turned on by the normally applied voltage. The array is programmable by means of a single photomask.

Abstract: A method for fabricating a semiconductor device having a pair of laterally spaced metal contacts adjacent a source and a drain, respectively, both contacts being located on a principal surface of a monocrystalline semiconductor, the contacts being separated by a groove therebetween. An edge of each of the contacts is extended in a cantilevered fashion over the groove, and a channel for the semiconductor is located under the groove. First and second laterally spaced Schottky-barrier gates are located in the groove adjacent the channel. In the method, the two Schottky-barrier gates are formed by deposition of a wide single gate onto a principal flat surface of the groove. The wide single gate is divided lengthwise into two separate Schottky-barrier gate conducting means by removing a portion of the gate through a photolithographically defined slot in a layer of a resistant means such as a photoresist or an ion-beam resist.

Abstract: A high resolution fluorescent screen including an amorphous coating of fluorescent dye on a substrate transparent to visible light is used to enable an observer to examine photomasks of the type used in manufacturing integrated circuits by using ultraviolet light. The screen converts ultraviolet light passing through the photomask into visible light. The screen is comprised of a transparent substrate having a high resolution amorphous coating of fluorescent dye in a binder on one side. Alternatively, a transparent substrate including a fluorescent material, such as uranium glass, may be used. On the other side of the substrate an ultraviolet blocking filter is applied to prevent ultraviolet light from injuring the eye of an observer using the screen.

Abstract: A technique for optically monitoring the undercutting of a layer of material being selectively etched beneath a pattern of masking material in an etchant comprises forming on a layer of the material being etched a diffraction grating pattern including spaced strips of masking material having a strip width W, exposing the diffraction grating pattern, while positioned in the etchant, to a beam of monochromatic light, whereby the grating pattern together with the layer of material therebeneath functions as a relief pattern which diffracts the beam of light into diffracted beams of various orders, and then monitoring certain of said diffracted beams to determine when a sharp decrease in the intensity thereof occurs, such a sharp decrease indicating an undercutting equal to a distance of W/2.

Abstract: A novel package for semiconductor components is disclosed. The package eliminates the need for covers or plugs at both ends of a hollow body wherein the components are placed. The novel package is easily adapted to provide anti-static protection for components susceptible to damage from electrostatic discharges across the terminals thereof.

Abstract: A semiconductor integrated circuit device which may be utilized as a Darlington circuit having an input stage and an output stage is disclosed. The Darlington may be characterized as having an increased isolation between the input stage and the output stage.

Abstract: A method for producing a pattern on a semiconductor wafer during the fabrication of semiconductor devices, including integrated circuits is disclosed. A master is pressed into a layer of moldable material which is on the wafer surface to define a pattern of at least one relatively thin region and relatively thick regions therein with a high degree of definition. Thereafter the whole layer is treated, for example, to remove, by etching for example, a relatively thin region to expose a portion of the wafer surface, the relatively thick regions remaining on the wafer surface.

Abstract: A semiconductor device comprising a plurality of cells is disclosed. Each cell contains at least one bi-polar transistor and a diode serially connected to the base of the transistor therein. Each cell is connected in parallel relation with each other cell. The diode in each cell is located in close proximity to the transistor therein so that the thermal gradient therebetween is small.

Abstract: Low resistance substrate contacts extending through the source region of an insulated gate field effect transistor (IGFET) will reduce parasitic bipolar effects in an integrated circuit. Such low resistance contacts may be made by diffusing impurities of a type opposite to the conductivity type of the source region through spaced areas of the source region thereby to provide low resistance paths between all points in the source and the underlying substrate. The low resistance contacts prevent large voltage drops in the substrate underlying the source thereby preventing "latch-up" of the parasitic devices formed during the manufacture of the integrated circuit.