Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.

Abstract: A semiconductor PROM containing a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16) is fabricated by a process in which the insulating region serves as a mask to control the lateral extents of the dopants utilized to define the diodes. The intermediate cell regions are ion implanted to obtain maximum dopant concentration near their mid-points. This facilitates programming operation.

Abstract: A circuit capable of simulating a transistor or a semiconductor diode with controllably adjusted voltage characteristics contains a main transistor (Q0). An input voltage (V.sub.CS) to a control system (8) is amplified with a gain set by a pair of resistors (R1 and R2) to produce a control voltage (V.sub.C) for the transistor. This downscales the forward voltage characteristics of the circuit from those of the transistor. A floating power supply (10) in series with the control electrode of the transistor permits upscaling or further downscaling of the circuit voltage range.

Abstract: A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the transconductance of the circuit as it is switching.

Abstract: A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.

Abstract: An input portion (4, 6) of a differential amplifier circuit amplifies a differential input signal to produce an amplified signal between a pair of terminals. A summing section contains two complementary pairs of like-polarity amplifiers (13, 14 and 19, 20). Each has a first flow electrode, a second flow electrode, and a control electrode. A substantially constant bias voltage is supplied to the control electrodes of the first pair (13, 14) whose second electrodes are respectively coupled to the second electrodes of the second pair (19, 20). Their first electrodes are respectively coupled to the terminals and to corresponding impedance elements (11, 12). The control electrodes of the second pair are coupled together to receive a voltage dependent on the voltage at the second electrode of one (13) of the first pair so as to produce a representative output signal at the second electrode of the other (14) of the first pair.

Abstract: A NOR gate consisting of a set of input FET's (Q1.sub.1 -Q1.sub.M) has a clamp (12/ Q2) that, when at least one of the input FET's is turned on, clamps the logical low level of the gate output voltage at a value which is largely constant irrespective of how many of the input FET's are conductive.

Abstract: A portion (28) of photosensitive material is created by an underetching/shadowing technique in such a manner as to have an extremely narrow width.

Abstract: A steering circuit (10) in a differential amplifier having a pair of differentially arranged input amplifiers (A1 and A2) steers current from a pair of current sources (11 and 12) in such a way as to enhance slew rate without increasing offset voltage. The steering circuit is formed with a pair of steering amplifiers (A3 and A4) arranged in a differential configuration through a pair of resistors (R3 and R4).

Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Abstract: In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell.

Abstract: A semiconductor device contains first and second semiconductive regions (43 and 78) and first, second, and third semiconductive zones (59/61, 79, and 71) of opposite conductivity type to the regions. The first zone adjoins an insulating layer (45/46/47/48/63) along an upper surface of the first region. The second region extends to the upper surface through a window in the insulating layer. The second zone adjoins the second region below the window and is spaced apart from the third zone which extends to the upper surface. The zones and insulating layer upwardly and laterally enclose the second region. A first segment (59) of the first zone is continuous with the third zone and at least partly adjoins the lateral edge of the insulating layer located apart from the window.

Abstract: A bipolar gate has an output transistor (Q5) that switches in response to the voltage at an emitter of a drive transistor (Q2 or Q10). An active pull-off circuit (14) discharges the base of the output transistor (Q5) when it turns off. The discharge path is provided through a pull-off transistor (Q7) whose collector is coupled to the base of the output transistor. The switching of the pull-off transistor is regulated with a control circuit containing a trigger circuit and a bias circuit. The trigger circuit is coupled between the bias circuit and a collector of the drive transistor. A "kicker" circuit formed with an input transistor (QC1) and a voltage reference (18) speeds up the switching of the drive transistor.

Abstract: A bipolar input circuit for regulating the current/voltage level at the base of a switching transistor (QA) provides a capacitively-controlled discharge path from the base through a discharge transistor (QC) when an input signal (V.sub.I) makes certain voltage transitions. The base of the switching transistor responds to the voltage at an emitter (E1) of an input transistor (QB) which has another emitter (E2) coupled to the base of the discharge transistor. Its base is further coupled to a capacitor (C) which controls the discharge path.

Abstract: A bipolar signal translator contains a pair of transistors (Q1 and Q2) arranged as a current mirror with their emitters coupled to a voltage supply (V.sub.EE) by way of a pair of impedance elements (R4 and R5) that improve stability. Their collectors are coupled through another pair of impedance elements (R1 and R2) to an input transistor (Q4 or Q5) and to a device circuit (D1 and D2, D3 and D4, or Q4). The collector of one of the current-mirror transistors (Q2) is coupled to the base of an output transistor (Q3) whose collector is preferably coupled through an output impedance element (R3) to a current-control transistor (Q6) that improves power utilization.

Abstract: A device for testing continuity and current leakage at leads of an electronic circuit such as an integrated circuit has a contact structure (16) having test terminals (T1-T28) for contacting the leads. A first and a second of the leads are power supply leads respectively contactable with a first and a second of the test terminals (T14 and T28 or T26). Continuity/leakage detection is done with one or more corresponding detection circuits (D1-D28). Each detection circuit has a channel along which both continuity and leakage are tested. A supply switching circuit (26) appropriately switches voltages between values suitable for continuity testing and values suitable for leakage testing.

Abstract: An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The minor portion has a lower net impurity concentration than the major portion and extends to a considerably lesser depth. An impurity is introduced into the major and minor portions to form a second region (24) of first type conductivity. An impurity is introduced into the second region to form a third region (30) of second type conductivity spaced laterally apart from the minor portion. Metallization is then performed to create at least one Schottky rectifying contact (32) with the major portion and ohmic contacts (38, 36, and 34) with the substrate and second and third regions.

Abstract: A bipolar impedance buffer contains an input transistor (Q1) whose emitter is coupled to that of a like-polarity intermediate transistor (QN). Its collector is coupled to the base of a like-polarity output transistor (QO), while its base is coupled to the collector of an opposite-polarity transistor (QP). A resistor (RN) coupled between the base and collector of the intermediate transistor significantly reduces the output settling time.

Abstract: A voltage reference for providing a reference voltage (V.sub.AB) between a pair of terminals (A and B) contains a diode (D) and a bipolar transistor (Q) whose base is coupled to one electrode of the diode. The collector of the transistor is coupled to a node (C) between one of the terminals (A) and the other electrode of the diode. The emitter of the transistor is coupled to the other terminal (B).

Abstract: A differential amplifier circuit contains a pair of complementary input portions (3, 5 and 4, 6). The input portions amplify a common differential input signal to produce corresponding amplified differential signals which are supplied to a summing section that operates as a modulated current mirror to produce an output signal representative of the input signal. The summing section contains a pair of like-polarity first and second amplifiers (13 and 14) and a pair of like-polarity third and fourth amplifiers (19 and 20) complementary to the other amplifiers. A pair of impedance elements (11 and 12) are coupled between a first voltage supply (ground reference) and the third and fourth amplifiers. A pair of current sources, typically impedance elements (8 and 9), are coupled between a second voltage supply (+B) and the first and second amplifiers.