Abstract: A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

Abstract: A signal translator for converting an input voltage (V.sub.I) into an output voltage (V.sub.O) at a different level contains a primary element stack (10) and a similarly-configured image element stack (12), both coupled between the sources of a potentially first variable supply voltage (V.sub.CC) and a normally constant second supply voltage (V.sub.EE). A reference voltage (V.sub.R) is supplied to both a primary-stack transistor (Q2) which provides the output voltage and an image-stack transistor (Q4) which provides a feedback signal (V.sub.F). A feedback circuit (14) formed with an amplifier (16) and a shifting circuit (18) response to the feedback signal to supply the reference voltage at such a value as to compensate the output voltage for changes in the first supply relative to the second supply voltage is particularly useful for CTL-to-TTL logic.

Abstract: A bipolar differential amplifying circuit contains a pair of input transistors (3 and 4) for receiving a differential input signal, a pair of differentially-configured first and second transistor circuits (5 and 6) coupled to the input transistors, and a subtracting circuit (11 and 12) for comparing the sum of the currents through first collectors (5C.sub.1 and 6C.sub.1) of the transistor circuits with the current through a second collector (6C.sub.2) of the second transistor circuit to generate an output signal representative of the input signal. A PN diode (13) is coupled to a second collector (5C.sub.2) of the first transistor circuit. The voltages at the collectors are very close, thereby yielding a high common-mode rejection ratio for the input signal.

Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Abstract: A TTL circuit having a pair of current sources (R2/V.sub.CC and R2/V.sub.CC) and a pair of transistors (Q1 and Q2) arranged in a standard TTL input/inverting configuration has hysteresis at the input signal (V.sub.X) for providing noise protection. A hysteresis circuit (10) suitably containing another current source (R3/V.sub.CC) coupled to the base of the inverting transistor (Q2) and a rectifier (12) coupled between the collector of the inverting transistor and the current source (R1/V.sub.CC) coupled to the base of the input transistor (Q1) provides the hysteresis at the circuit switching points.

Abstract: A method of manufacturing a semiconductor device having two juxtaposed regions (12, 16) of opposite conductivity types which adjoin a surface and which together constitute a p-n junction (9) which is preferably perpendicular to the surface and the doping concentration of which decreases towards the surface. According to the invention n-type and p-type buried layers (2, 6) are provided beside each other on a semiconductor substrate (1) and on said layers a high-ohmic epitaxial layer (7) is grown. By heating, the dopants diffuse from the buried layers through the whole thickness of the epitaxial layer and into the substrate. With suitably chosen donor and acceptor atoms (for example boron and phosphorus in silicon) n and p-type regions (12, 16) are formed in the epitaxial layer and form a p-n junction (9) perpendicular to the surface by compensation of the lateral diffusions from the buried layers.

Abstract: A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (.0..sub.1) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (.0..sub.2) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.

Abstract: A semiconductor device is fabricated by a process in which an aperture (4) is an insulating layer (3) along a surface (2) of a semiconductor body is utilized in defining the lateral extents of zones (6, 7, and 8) in a circuit element of the device. In particular, the insulating layer is first provided with the aperture along the surface. A semiconductor layer (5) is formed on the insulating layer, including the portion within the aperture. Using the edge of the insulating layer along the aperture as a masking edge, a pair of opposite-conductivity dopants are introduced selectively into the aperture and a third dopant is introduced through all of the aperture into the body. The third dopant may be introduced into the body before the semiconductor layer is formed.

Abstract: A logic circuit in which (1) a first bipolar transistor has a base, an emitter, and a collector coupled to a voltage/current source, and (2) a second bipolar transistor has a base coupled to the emitter of the first transistor, an emitter coupled to a constant voltage source, and a collector coupled to the voltage/current source contains operational control circuitry for preventing the second transistor from either turning off or normally going into deep saturation. Each transistor is typically an NPN device. The operational control circuitry may then comprise (1) first circuitry for providing current from the voltage/current source in a single current-flow direction to the collector of the second transistor and (2) second circuitry for providing current from the first circuitry in a single current-flow direction to the base of the second transistor. Optimally, the first circuitry prevents the second transistor from ever going into deep saturation.

Abstract: A method of manufacturing integrated circuits by means of a multilayer mask.Etching of the layers of the mask comprises a lateral etching of the bottom layer so that at the edge of the auxiliary layer edges appear which are removed partly prior to forming an insulating layer and partly after the formation thereof, after which a remainder of a mask portion is also removed as a result of which removal apertures for the formation of zones are determined.

Abstract: In manufacturing a semiconductor device, a semiconductor body (2) is first provided with a first insulating layer (3,4) having a homogeneous dielectric thickness. A first conductor pattern (5) of polycrystalline silicon is then provided on the first insulating layer. A second insulating layer (6) is formed by oxidation of the first conductor pattern in such manner that the dielectric thickness of the first insulating layer remains approximately constant. Insulating paths (8) are then formed in spaces below edges (9) of the second insulating layer by successive deposition and etching steps. During the deposition step, a temporary layer is deposited to a thickness exceeding half the height of the spaces. During the etching step, the temporary layer is removed from the second insulating layer. Finally, a second conductor pattern (7) is provided on and beside the second insulating layer.

Abstract: An X-ray fluoroscopy device comprises a television camera for locating the irradiation field. This camera forms an optical image of the object to be irradiated. This image can be displayed on a television monitor, together with an image of the irradiation field, so that the position of the irradiation field within the object can be directly observed.

Abstract: Apparatus for examining objects includes a group of X-ray sources, which are activated group-wise by a generator. A group of sub-images are separately projected onto a photographic film. During a subsequent step, the film is re-imaged with the aid of an optical lens matrix the lenses in the matrix are arranged in a manner similar to the X-ray sources.

Abstract: A mechanism is provided for varying the distance between a detector and a measuring crystal in an X-ray spectrometer. The crystal is arranged on a rotatable shaft and the detector is arranged on an arm which can perform a circular movement about the crystal shaft. The crystal shaft and the detector arm are coupled so that a rotation of the crystal shaft through an angle .theta. is accompanied by a rotation of the detector arm through an angle 2.theta.. A first pulley having a radius r is mounted on the crystal shaft and a second disc having a radius 2r is rotatably mounted on the crystal shaft. A belt or cord is guided over each one of two guide rollers. One end of each of these belts is permanently connected to the first pulley, while its other end is permanently connected to the second pulley.

Abstract: A field effect transistor of the V-MOST type in which the channel region comprises a more highly doped part which adjoins the source zone and a lower doped part which surrounds said region, said channel region adjoining the surface and surrounded by an insulation diffusion. The lower-doped part is depleted from the pn junction with the low-doped drain region up to the surface at a voltage which is lower than the breakdown voltage.