Abstract: A surface-emitting AlGaInP LED is disclosed.

Abstract: A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

Abstract: A system for increasing the security of a computer system, while giving an individual user a large amount of flexibility and power. To give users the most power and flexibility, a standard object that has the capability to embed objects is used. To allow users even more flexibility, a standard object tracking mechanism is used that allows users to distribute multiple encrypted embedded objects to other individuals in a single encrypted object. By effecting compartmentalization of every object by label attributes and algorithm attributes, multi-level multimedia security is achieved.

Abstract: A simple-structured pressure sensitive resistor cell which permits the setting of a stylus pressure detecting threshold value VT and a stylus pressure detecting threshold value setting method therefor. A midtap T of a series connection of two or more resistors R1, R2 is connected to an input terminal of an A/D converter and a potential voltage divided by the resistors at the midtap T is defined as the stylus pressure detecting threshold value VT. Therefore, the stylus pressure detecting threshold value VT can be adjusted simply by changing the resistance value of either one of the resistors.

Abstract: An image processing apparatus in which an original image read by a scanner is rotated by an angle of 90.degree. to be output. One-page image data output from the scanner is stored in a memory on a dot-by-dot basis. The memory is adapted to read therefrom and write therein dot data along a dot array and along a line array. A first read-out operation in which the dot data are successively read out of the memory along the dot array and a second read-out operation in which the dot data are successively read out of the memory along the line array are alternately switched every time reading a one-page image of the document original is competed. Dot data newly generated is written in a storage area from which the previous dot data has been read out at substantially the same time when the previous dot data is read out of the memory.

Abstract: A method of fabricating a via, that reduces contact resistance between two conductive layers. A conductive layer is formed at the periphery of a top surface of a gate. An insulating layer is formed over the gate, and is etched to form a via exposing the top surface of the gate and portions of the conductive layer. The top surface of the gate and the exposed conductive layer form a step profile, which provides extra contact area without increasing the lateral extent of the via.

Abstract: A miniature optical head for optical disk drive units is disclosed. The head assembly comprises a polarization light-splitter means having a block-shaped body. A laser light source generates a laser light beam at a predetermined wavelength and illuminating into the block body of the polarization light-splitter means. A first quarter-wavelength light plate means arranged at a side surface of the block-shaped body of the polarizing light-splitter means is placed opposite the laser light source. A reflective diffraction grating arranged further external to the first quarter-wavelength light plate means is used for reflectively diffracting the laser light beam. A second quarter-wavelength light plate means is arranged to a surface of the block-shaped polarizing light-splitter means in a plane perpendicular to the first quarter-wavelength light plate means. A holographic optical element is arranged on a side surface of the block-shaped body opposite the second quarter-wavelength light plate means.

Abstract: A DRAM with a vertical channel structure is manufactured with an epitaxial silicon layer, above a silicon substrate, and is preformed with a source region. A well is formed in the epitaxial silicon layer. A trench is formed to penetrate into the source region. A first insulating layer is formed on a surface of the trench and then a gate is formed, almost completely filling up the remaining space in the trench. A drain region is formed inside the well. A storage capacitor is formed above the drain region.

Abstract: Special sheets to be handled differently from normal sheets are accommodated in a specific sheet feeding deck such that a predetermined operation or presentation associated with reproduction procedure is permitted or prohibited for the special sheets in the specific sheet feeding deck. For example, if the production of two-sided copies is prohibited for a specific sheet feeding deck which accommodates sheets to be used again, the sheets are not automatically selected during the production of two-sided copies even if they are of the same size as a document original. This ensures erroneous handling is prevented, such as image forming on both sides of the special sheets in the specific sheet feeding deck.

Abstract: A high-strength transportation frame for carrying wafer boats between processing stations in a semiconductor fabrication facility includes a pair of transporting rods each having a corresponding grip portion, a number of fixing elements, and a pair of connecting rods. The connecting rods extend parallel to each other and are connected to each of the pair of transporting rods at remote ends thereof, the connections being secured by the fixing elements.

Abstract: A process for fabricating load resistors for memory cell units of semiconductor SRAM device. The process includes providing a silicon substrate containing an intermediate semiconductor device with a gate structure and source/drain regions for a transistor of the cell unit. A first dielectric layer is then formed over the surface of the silicon substrate, the first dielectric layer having opening vias connecting to the gate electrode of the gate structure and a source/drain region. A polysilicon layer is then deposited. The polysilicon layer is then patterned by etching to form a discontinuity between the gate electrode and one of the source/drain regions. An oxidation resistant layer is formed and patterned for exposing regions of the polysilicon layer designated for the formation of the load resistors. An oxide layer is formed over the surface of the exposed portions of the polysilicon layer, so that the thickness of the designated regions of the polysilicon layer underneath the oxide layer is reduced.

Abstract: A clock recovery circuit receives an input signal having an eye pattern and takes differences at certain intervals to generate a differential signal. A set of comparators detect timings at which the differential signal matches different levels, and generate pulse signals at these timings. A gate-signal generating circuit detects timing relationships among these pulse signals, and activates a gate signal when pulse sequences having certain timing relationships are detected. A delay circuit delays one of the pulse signals to create a delayed signal. A gate circuit outputs the delayed signal as a timing signal when the gate signal is active. A phase-locked loop generates a clock signal synchronized to the timing signal.

Abstract: A process for fabricating a storage capacitor for memory cell units of a DRAM memory device to achieve an increased capacitance value. The process includes first forming a transistor including a gate, a source region, and a drain region on the silicon substrate of the device. The gate includes a first polysilicon layer covered by an insulating layer. A silicon nitride layer is formed covering the transistor and a silicon oxide layer is formed on the silicon nitride layer. A contact opening is formed in the silicon oxide layer and the silicon nitride layer which exposes the surface of the transistor drain/source region. The silicon oxide layer has an edge portion extending toward the cavity of the contact opening more than the edge of the silicon nitride layer below it extends. A second polysilicon layer is then formed in the contact opening, covering the exposed drain region, the gate, and the edge portion of the silicon oxide layer and the silicon nitride layer.

Abstract: A power supply supplies an a-c power as primary electric power and a d-c power as secondary electric power. A converter converts the primary electric power, for example, 100 VAC into the secondary electric power, for example, +5 VDC and +24 VDC. The primary electric power is used to heat, for example, a heat roller of a printer. An abnormal-temperature detector outputs a detection signal when the temperature of the heat roller heated by the primary electric power exceeds a predetermined temperature. A controller causes the converter to draw an additional current from the primary electric power in response to the detection signal so that a current drawn from the primary electric power exceeds a predetermined current. An abnormal current interrupter shuts down the current drawn from the primary electric power when the current drawn from the primary electric power exceeds the predetermined current. The power supply may have an abnormal current detector instead of the abnormal-temperature detector.

Abstract: A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. the semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths am set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable signal and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

Abstract: An optical device is disclosed which comprises a base including a lower cylindrical base member having a common central line and a first diameter and having top and bottom surfaces, a first electrode layer formed on the top surface of the lower base member, a dielectric layer formed on the first electrode, a second electrode layer formed on the dielectric layer, and an upper base member formed on the second electrode layer, the upper base member including a first cylindrical member having the common central line and the first diameter and having top and bottom surfaces, the bottom surface of the first cylindrical member faced on the second electrode layer and a second cylindrical member having the common central line and a second diameter smaller than the first diameter and having a top surface and a bottom surface faced on the top surface of the first cylindrical member; elongated leads supported by the base, the leads being elongated so as to protrude from the bottom surface of the lower base member; a ring

Abstract: A high-voltage MOS (metal-oxide semiconductor) device and a method for fabricating the same is provided. The high-voltage MOS device features the forming of trench-type source/drain structure in substitute of conventional highly doped structure formed by implantation. The improved structure allows the source/drain regions to occupy a small area for layout on the chip. In addition, the forming of the trench-type source/drain structure in N-wells allows an increased current path from the source/drain regions to drift regions, meaning that the conductive path for the current is not limited to only the junction between the source/drain regions and the drift regions as in conventional structures. Moreover, since the trench-type source/drain structure extends upwards from the inside of N-wells to above the surface of isolation layers, metal contact windows can be formed above the isolation layers, thus preventing the occurrence of leakage current.

Abstract: A ROM device with a 3-dimensional memory cell structure that allows a high packing density of memory cells in the ROM device. The ROM device includes a silicon substrate having a plurality of parallel trenches formed thereon. These trenches define mesa regions therebetween. Source/drain regions are then formed on the trenches and the mesa regions. Sidewall spacers are formed on lateral sides of selected trenches. A gate oxide layer is then formed over the silicon substrate. Gate layers are then formed on the gate oxide layers along a direction perpendicular to the trenches. These gate layers serve as word lines. The bit lines over the trenches and the mesa regions utilize channel areas between each neighboring pair of source/drain regions in the horizontal direction to define a plurality of horizontal memory cells at intersections with the word lines. Each horizontal memory cell can be programmed by ion implantation.

Abstract: A gain control circuit according to the present invention comprises an amplifier circuit for controlling gain thereof to amplify an input signal and a control circuit. The amplifier circuit includes an input terminal for inputting the signal, a first transistor having a drain electrode connected to a first potential through a first resistive means and a source electrode connected to a second potential, and an output terminal connected to a first electrode and varies the value of a resistance between the source and drain of the first transistor based on the signal supplied to the input terminal. The control circuit is composed of a second transistor having a source electrode connected to the source of the first transistor, a drain electrode connected to the drain of the first transistor and a gate electrode supplied with a control signal and varies the value of a resistance therebetween based on the control signal supplied to the gate electrode.

Abstract: A process for making a good-tasting alcoholic or nonalcoholic beverage from pine needles. Pine needles are boiled in water with licorice root, cinnamon powder, black beans, and Ganoderma Lucidum. The mixture/solution is cooled in the ambient environment, reheated, and then filtered. The resulting beverage retains the beneficial qualities of a pine needle beverage, while the bitter taste and odor of terpenes are substantially eliminated.