Abstract: A multiple-chip IC package used to contain a number of chips therein is provided. The multiple-chip IC package includes a leadframe, at least one IC chip mounted on the leadframe, and at least one dummy chip mounted on a second area on the leadframe. On the dummy chip, there is provided with a plurality of bonding pads which serve as intermediate bonding pads between the chips and the pins on the leadframe so that any two connecting points are connected by a number of straight wires via the dummy chip. This allows the wire bonding process to be much easier to conduct. Further, the method for assembling this multiple-chip IC package includes a first step of mounting the chips on a leadframe; a second step of mounting at least one dummy chip having a plurality of bonding pads thereon on a selected area on the leadframe; and a third step of conducting a wire bonding process to interconnect between the chips and the pins.

Abstract: A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.

Abstract: A MOS device and method of fabricating the same, wherein the source/drain region has polysilicon trench structure which are formed by self-alignment using silicon oxide layers as masks. The source/drain regions extend to the field oxide layer and/or above the gate. Therefore, contacts can be formed on source/drain conductive regions above the field oxide layer.

Abstract: A method of making a flash memory cell includes patterning a series of layers over a semiconductor substrate of a first conductivity type to form a gate electrode structure. A first ion implantation procedure is performed to introduce a first impurity of a second conductivity type into the semiconductor substrate and form a heavily-doped source region and a heavily-doped drain region. A second ion implantation procedure is performed at a tilt angle of 25.degree. to 45.degree., to introduce a second impurity of the second conductivity type into the semiconductor substrate and form a pair of asymmetric lightly-doped regions, with one of the asymmetric lightly-doped regions surrounding the heavily-doped source region, and the other of the asymmetric lightly-doped regions beneath the heavily-doped drain region. An insulating spacer is formed on sidewalls of the gate electrode structure.

Abstract: A method of forming a bit line of a dynamic random access memory. An insulating layer is used to cover the source/drain region in a substrate. A trench is formed in the insulating layer above the source/drain region. Then, a portion of the insulating layer inside the trench is removed to form an opening which exposes the source/drain region. A conductor is used to fill the trench and the opening so as to form a bit line and a metal plug, respectively.

Abstract: The portable type electronic apparatus of the present invention is provided with an apparatus body having an apparatus side connection contact, a card holder, having guide channels for guiding an IC card to a specified position. One end side is freely rotatably attached to the apparatus body via an axis, for retaining an IC card by causing a card side connection contact to come into contact with the apparatus side connection contact, and a stopper, having edges respectively provided at the apparatus body and the card holder, for unfolding a wall between the card holder and the apparatus body accompanying rotation of the card holder.

Abstract: A test pattern simulates conductors and interconnections of conductors of a multi-layer semiconductor device that may be subject to damage from electromigration. Test pattern elements are connected in a series circuit with two connection points for applying a test current to the elements. A break in this circuit or an increase in resistance during the test signifies that electromigration has damaged the test pattern and that the operating components of the device may have manufacturing defects that make them susceptible to electromigration. Probe points can be provided for testing particular parts of the series circuit. The pattern has at least one conductive stripe or other element in each layer of the device and it has interconnecting vias between these elements through one or more intervening layers of insulation where corresponding layer-to-layer interconnections are made in the operating components of the device. On the surface of the device, diffusions form part of the circuit path.

Abstract: A surface treatment material used in fusing dental porcelain, containing powder of gold terpene sulfide, is applied and sintered on a metal frame. Then, the terpene and sulfur oxidize to suppress oxidation of gold and the like. A surface treatment layer having no coat, is thus formed on the surface of the metal frame with the alloy component of the metal frame and gold being bonded and combined with each other in a diffusion and solid solution manner. Then, it is fused with a dental porcelain built up on the surface of the metal frame on which the surface treatment layer is formed.

Abstract: A printing data transmitted from a host computer is stored in a receiving buffer. An editorial unit receives the printing data in the receiving buffer in each one line and writes into a page buffer after compressed. An expansion unit reads out the printing data in the page buffer and deploys them into a band buffer as a raster data. An engine unit performs printing in accordance with the raster data in the band buffer. The editorial unit compresses the printing data of each line up until the preset line N with plural types of compression techniques and computes compression rates for each line. A compression technique to be applied is determined in accordance with the compression rates. The printing data of each line up until those of the preset line X are compressed by the determined compression technique. A determination of the compression technique is repeated in every completion of the printing data processing for the X lines.

Abstract: A decorative balloon assembly including a number of connected balloon units. Each balloon unit includes a number of globe-shaped balloon elements arranged in an annular fashion. Each of the balloon elements is linked to adjacent balloon elements by air passageways. One of the balloon elements includes an air inlet valve for inflating the balloon elements. Flexible sheet material connects the balloon elements in the center of the annular arrangement. The flexible sheet includes a center opening through which a connector may be inserted to link a number of balloon units. The connector may be a rod, so that a rigid standing balloon assembly may be constructed. Alternatively, the connector may be a rope, so that the balloon assembly may take a flexible shape, such as an arch to be hung from a ceiling.

Abstract: A raceway box with replaceable cable and connector receptacles is provided. The raceway box allows easy replacement of various types of connectors when necessary. Further, the raceway box can provide inlet/outlet openings in various directions based on on-site requirements. The interior space of the raceway box is extendible so as to accommodate a large volume of interconnecting cables and wires. The raceway box is composed of a base unit, a plurality of inserts including cable raceway inserts and connector raceway inserts inset on the lateral sides of the raceway box, and a socket panel covering the base unit. The base unit includes a chassis having a plurality of side pieces mounted substantially upright on the edge of said chassis. These side pieces define a corresponding number of receptacles therebetween. The cable raceway insert is used to receive at least a cable into the raceway box, and the connector raceway insert is used to mount one connector therein.

Abstract: In a flextensinal transducer a drive stack provided inside the oval shell has a strain compensator that has a cylinder and piston. The cylinder is provided in the oval shell, and the piston is stiffly attached to the end of the drive stack. Inside the cylinder, the piston can move along the major axis of the oval shell. When the flextensional transducer is sunk into the water, the oval shell is distorted to extend along the major axis. Then the cylinder and the piston moves relatively to each other to compensate for the distortion.

Abstract: In a photoelectric sensor, a photosensitive device is mounted on a substrate and outputs an electric signal corresponding to light incident thereto. A casing holds the substrate in a bore formed therein and includes a light guide portion formed of an optically transparent material for conducting incident light to the photosensitive device. A light emitting device is also mounted on the substrate for emitting light in response to a current input thereto. A seal member is molded to air-tightly seal the light emitting device and photosensitive device except for a light guide portion included in the light emitting device and a light guide portion included in the photosensitive device.

Abstract: A method of fabricating a semiconductor memory device having a capacitor. First, a first insulating layer is formed on a substrate to cover the transistor. Next, a second insulating layer and a first conductive layer are formed in order. The first conductive layer only covers a portion of the second insulating layer to form a branch-like conductive layer. Then, a third insulating layer is formed. An opening is next formed. A second conductive layer is filled into the opening and therefore electrically connected to the source/drain region of the transistor to form a trunk-like conductive layer. Next, the second and the third insulating layers are removed. After a dielectric film is formed on the exposed surfaces of the first and second conductive layers, a third conductive layer is formed on the dielectric film to form an opposed electrode.

Abstract: An apparatus and method for implementing a supplementary column structure for supporting a raised floor. The apparatus includes a number of fixed supporting columns above a lower floor to support at least one raised floor. Each fixed supporting, column has two ends, one of which is attached to a base block fixed to the lower floor while the other end is attached to all upper connecting block supporting the raised floor. The method of adding the supplementary columns includes first choosing two fixed supporting columns and installing a horizontal beam with a U-shaped groove between the two fixed columns. At least one supplementary column is then provided, each supplementary column being attached to an I-shaped slidable base block enclosed by the grooved horizontal beam at its one end, and to an upper connecting, block supporting the raised floor at its other end. The supplementary column can then slide along the groove of the horizontal beam until a desired location is reached.

Abstract: A write-control circuit including a pulse processor and a waveform shifter is disclosed. The pulse processor is provided for processing a first waveform. When the first waveform has a bandwidth wider than a first delay, the waveform goes through the pulse processor without change. Otherwise, a second delay is added to trailing edge of the first waveform. The waveform shifter is provided for shifting the output waveform of the pulse processor as a second waveform. The pulse processor consists of a pulse generator, a trailing edge delay circuit, a NOR gate and an inverter. The pulse generator, which generates a finite-length pulse by the first waveform, includes a delay chain and a NAND gate. The delay chain may consist of an odd number of delay units. The trailing edge delay circuit includes an even number of delay units and a NAND gate for adding the second time delay to the trailing edge of the finite-length pulses.

Abstract: A MOS transistor array structure for an electro-static discharge protection circuit in a semiconductor integrated circuit device, having dispersed parallel discharge paths. The MOS transistor array includes an n-well formed in a silicon substrate of the fabricated semiconductor device. A first dispersed drain region is formed in the n-well, and a source region is formed in the silicon substrate. A second dispersed drain region is formed in both the silicon substrate and the n-well. A gate of the transistor array is formed on the silicon substrate, and a first field oxide region is distributed at least partially in the dispersed drain region, so as to improve the even distribution of electric current in the event of an electro-static discharge. The transistor structure is compatible with a silicided process of device fabrication for fast device operation. Fabrication of the structure does not require additional procedural steps for achieving this compatibility.

Abstract: A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers.

Abstract: A process for fabricating memory cells of flash memory devices that requires lower voltages between the drain and source regions when storing or erasing data, and avoids the punch-through problem associated with conventional flash memory devices having a high device density. The process includes forming successively on the surface of the silicon substrate a tunnel oxide layer, a floating gate layer, a dielectric layer, and a control gate layer. A portion of the tunnel oxide layer is exposed and unshielded. An ion implantation procedure is then applied to the silicon substrate to form a source region and a drain region. Sidewall spacers are then formed on the sidewalls of the control gate layer, the dielectric layer, the floating gate layer, and an unexposed portion of the tunnel oxide layer.