Abstract: A microprocessor with an execution stage (26) including a plurality of execution units and an instruction memory (32) for storing instructions. The microprocessor further includes circuitry for retrieving (14) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (30) for storing a plurality of information fields (30r) corresponding to a branch instruction. The information fields include at least a target instruction address (Tn), a prediction field (Pn) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPAn) indicating accuracy for past prediction fields.

Abstract: An improved damping modulation circuit (140) for a transponder (14) receives energy transmitted from a transmitter/receiver antenna (16) to produce a unique recognition signal in the transponder. The improved damping modulation circuit (140) includes a high fieldstrength circuit (152, 160, 174) that protects full-duplex transponder (14) from over-voltage through the use of voltage limiters (132), while still providing power to transponder (14). Low fieldstrength circuit (152) activates only minimal circuitry to provide the highest possible amount of power to full-duplex transponder (14). Medium fieldstrength circuit (152, 160) increases the fieldstrength in full-duplex transponder (14) for establishing a sufficient amount of current flow for proper modulation using only a medium amount of transponder (14) circuit elements.

Abstract: This is a method of forming mechanically robust vias and entrenched conductors on a dielectric layer (which dielectric layer is on an electronic microcircuit substrate which vias and entrenched conductors are electrically connected to a conductive area on the surface of the substrate) and a structure formed thereby. Generally some of the dielectric layers added above the microcircuit comprise a porous dielectric having a desirable low dielectric constant but low mechanical robustness.

Abstract: A method of tuning the resonance frequency of a transponder to a target frequency is described, wherein a transponder comprises a film antenna with an IC (IC) mounted to the film antenna (L) and an integrated resonance capacitor (C) is part of a IC. During testing of IC at chip probe to determine the pass/fail of the IC, the integrated resonance capacitor (C) is measured and the value is stored with the pass/fail data of the wafer map. Then after mounting a passed IC (IC) to a film antenna (L) with variable inductance, retrieve the integrated resonance capacitance value from the wafer map and calculate the amount of inductance necessary to achieve the target frequency. Tune the film antenna (L) to achieve the necessary inductance, measure the transponder resonance frequency, and compare the transponder resonance frequency to the target frequency.

Abstract: An electronic system 8 is disclosed herein. The system includes circuitry 10 for processing a signal and a plurality of antennas 12a-12b. A plurality of switches 22a-22b are also included. Each of the switches 22a-22b is coupled between the processing circuitry 10 and a corresponding one of the antennas 12a-12b. Each of the switches 22a-22b includes first and second power MOSFETs where the source of the first MOSFET is coupled to the source of the second MOSFET. The system further includes circuitry 28 for selecting of one of the plurality of switches 22a-22b to be on.

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.

Abstract: A system of vehicle identification with a first interrogator that uses a Lower SideBand (LSB) receiver to receive a modulated signal from a vehicle transponder and a second interrogator that uses an Upper SideBand (USB) receiver to receive another modulated signal. The two interrogators are adjacent to each other at a toll plaza, and operate at different carrier frequencies to force a signal frequency bandgap between communication signals in adjacent vehicle lanes.

Abstract: An error-correcting dynamic memory (100) which performs error correction (110) only during refresh or during the second (or subsequent) read of a burst read or during a writeback. Further, the memory may contain an error-correction-code-obsolete bit in addition to data bits and check bits in order to generate check bits during refresh and not during write. This provides error correction without read access delay or write delay at the cost of slightly more exposure to soft errors.

Abstract: A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations.

Abstract: A memory configuration (304) comprising a row array (302) having a plurality of rows. The memory configuration further includes a plurality of memory columns (C.sub.0 through C.sub.4). Each of the plurality of rows is constructed to communicate a plurality of signals along the plurality of memory columns and each of the plurality of memory columns provides a memory column output. Further, the memory configuration includes a plurality of output columns (OC.sub.0 through OC.sub.3). Each of the plurality of output columns is operable to output a data signal external from the memory configuration. Still further, the memory configuration includes an encoder circuit (308) and a decoder circuit (306, M.sub.1 through M.sub.4). The encoder circuit identifies an identified one of the plurality of memory columns.

Abstract: A dynamic multiplexer circuit (20) comprising an integer number N of data providing circuits (26, 28, 30), wherein the integer number N is greater than one. Each of the plurality of data providing circuits comprises a precharge node (26.sub.PN, 28.sub.PN, 30.sub.PN) to be precharged to a precharge voltage during a precharge phase, and a conditional series discharge path (26.sub.L and 26.sub.DT, 28.sub.L and 28.sub.DT, 30.sub.L and 30.sub.DT) conrected to the precharge node Each discharge path is operable in response to at least one enabling input signal (INPUTS.sub.26, INPUTS.sub.28, INPUTS.sub.30) to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node. Each of the plurality of data providing circuits further comprises an inverter (26.sub.INV, 28.sub.INV, 30.sub.INV) coupled to the precharge node and having an output for providing a second monotonic transitioning data signal.

Abstract: A logic circuit (18) comprising a first phase domino logic circuit (20) and a second phase domino logic circuit (22). Each of the domino logic circuits comprises a precharge node (20.sub.PN, 22.sub.PN), a coupling device (20.sub.PT, 22.sub.PT) which when conducting couples the precharge node to a precharge voltage (V.sub.DD) during a precharge phase, and a discharge path (20.sub.L and 20.sub.DT, 22.sub.L and 22.sub.DT) connected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase. Further, each of the domino logic circuits comprises an inverter (20.sub.IN, 22.sub.IN) coupled to the precharge node and providing an output responsive to a voltage at the precharge node. The output of the inverter of the first phase domino logic circuit is connected to control the conduction of the discharge path of the second phase domino logic circuit.

Abstract: A method of operating a microprocessor (12). The method first receives (64) a plurality of instructions arranged in a sequence from a first instruction through a last instruction. The method second identifies (66) a branch instruction as one of the plurality of instructions, wherein the branch instruction has a target instruction address. The method third determines two factors for the branch instruction, the first being a prediction value (72) indicating whether or not program flow should pass to the target instruction address, and the second being an accuracy measure (74, 76) indicating accuracy of past ones of the prediction value. The method fourth identifies a data fetching instruction following the branch instruction in the plurality of instructions. Lastly, the method issues a prefetch request (70, 78) for the data fetching instruction in response to the accuracy measure.

Abstract: A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an array of memory cells (12). The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODEBR SET 1-8), each having a plurality of wordline enable outputs (WL.sub.0 -WL.sub.225). Each of the plurality of wordline enable outputs corresponds to a respective one of the integer number N of wordlines and is operable to assert an enabling signal to the respective one of the integer number N of wordlines. Each of the plurality of predecoders includes a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3) a plurality of predecoder conditional series discharge paths (e.g., TA5.sub.0, TA6.sub.01, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets includes a plurality of decoder precharge nodes (e.g., PN.

Abstract: A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an N wordline array of memory cells (12). The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODER SET 1-8) having wordline enable outputs (WL.sub.0 -WL.sub.255). Each of the plurality of predecoders comprises a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3), a plurality of predecoder conditional series discharge paths (e.g., TA5.sub.0, TA6.sub.01, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets comprises a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub.0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub.31).

Abstract: A microprocessor (10) and system (2) are disclosed, in which capability for the detection and handling of modifications of instructions potentially in the pipeline is implemented. The microprocessor (10) includes a self-modifying code (SMC) unit (50) that includes a fetch address window maintenance unit (52), a write comparator (54) associated with each load/store unit (40) in the microprocessor (10) that performs writebacks to memory (16, 11, 5), and a shared write comparator (55). The fetch address window maintenance unit (52) includes a minimum latch (60) that stores the lowest fetch address since a pipeline flush or machine reset, and a maximum latch (62) that stores the highest fetch address since flush or reset, and updates the minimum and maximum latches (60, 62) upon detecting that the current fetch address (LASTFA) falls outside of the current window.

Abstract: A microprocessor (10) and system implementing the same is disclosed, in which stack-based register address calculation is performed in a single add cycle for instructions involving a PUSH operation. The microprocessor (10) includes a floating-point unit (FPU) (31) having a register stack (52.sub.ST) and a stack pointer (FSP), for executing floating-point instructions containing relative register addresses (REG) based upon the contents (TOP) of the stack pointer (FSP). The instructions may involve PUSH operations, in which an operand is added to the stack of operands in the register stack (52.sub.ST). Register addressing circuitry (125, 125') includes an adder (122; 122') for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction, and an adder/decrementer (120) for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction minus one, to account for the PUSH.

Abstract: A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an array of memory cells (12) aligned in an array. The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODER SET 1-8), each having a plurality of wordline enable outputs (WL.sub.0 -WL.sub.255). Each of the plurality of predecoders comprises a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3), a plurality of predecoder conditional series discharge paths (e.g., TA5.sub. 0, TA6.sub. 0, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets comprises a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub.0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub.31).

Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).