Abstract: Novel means of achieving increased security while still obtaining a low cost, manufacturable device are disclosed and claimed. The first mode of operation is the learn mode which provides means for initial checkout with no security. In the learn mode of operation, the interrogator and transponder may be switched to a predetermined error detection algorithm, i.e. CCITT(Start Mask, CCITT Mask), and certain information is programmed into the transponder memory. During programming, all the bits received from the interrogator are shifted through the preintialized CRC generator. In addition, once the transponder response is sent back to the interrogator, the response is also shifted through a preinitialized CRC generator within the interrogator(which could be a software implementation). Because neither the Cypher Key nor the Function Key are directly readable once programmed, an encryption must be performed to verify the proper Cypher Key and Function Key were programmed into the transponder's memory.
Abstract: A microprocessor-based data processing system (2) in which asynchronous bus transactions are performed is disclosed. The disclosed embodiments include one or more microprocessors (5) of the x86-architecture type, compatible with the P54C bus protocol, preferably Pentium-compatible microprocessors, as the central processing units (CPUs) of the system. A CPU (5.sub.r) requests an asynchronous bus transaction, in a first disclosed embodiment, by presenting a combination of control signals that is unused in conventional x86-architecture systems; the controller chipset (27) determines whether the transaction may be performed in an asynchronous manner, and later returns an acknowledge or non-acknowledge code to the requesting CPU (5.sub.r). The microprocessors (5) include certain pins, in this first embodiment, corresponding to conventional Pentium-compatible output pins but which now have receiver circuitry for receiving the acknowledge and non-acknowledge codes, along with the transaction identifier.
December 27, 1996
Date of Patent:
October 5, 1999
Texas Instruments Incorporated
Jonathan H. Shiell, Ian Chen, Robert W. Milhaupt
Abstract: A circuit (10) for producing a microprogram memory address (16). This circuit includes circuitry (18I, 18J) for selecting a plurality of condition codes. Additionally, the circuit includes logic circuitry (20) for producing a result by performing logic operations using as operands the selected plurality of condition codes. The result of the logic operations forms a first portion (LSB', or LSB' and NLSB') of the microprogram memory address.
Abstract: A method of preventing a response to a rouge poll message in an AVI system is presented. The method entails that during the transmission of the poll message from the interrogator to the transponder, wherein the poll message reflects off an undesirable position, thereby creating the origination of an undesirable poll message, i.e. a poll message which will be received by a wrong transponder, a jamming signal is also transmitted at the same frequency and from the point from which said reflected poll message originates. The jamming signal and the poll message create a rogue poll message as received by the transponder wherein at least one bit within the transmitted poll message is flipped. Transponders, upon receiving said rogue poll message, calculate the CRC and compare the calculated CRC with the received CRC. The rogue message should yield an invalid CRC, i.e. a CRC unlike the received CRC, and therefore, the transponder will fail to respond to the jammed poll message.
Abstract: A load target circuit (56) with a plurality of entries (56.sub.1). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.
Abstract: A corrected digital response signal is generated from a corrupted transponder response signal by receiving the response signal an odd number of times, greater than one, and sampling each received response signal a predetermined number of times. Then, the sample values from each transponder response signal are compared to one another and a majority sample value is obtained. The majority sample value is the value ordained by the majority and therefore represents the corrected response signal value. Alternatively, if time does not permit reception of more than one transponder response signal, additional response signals may be generated from the originally received response signal by shifting the received response by a predetermined number of samples to the right and by shifting the received response by a predetermined number of samples to the left to generate second and third response signals.
Abstract: A computer system including an arrangement for programmably assigning interrupts to a larger set of interrupt channels. The computer system includes a microprocessing unit ("MPU" 102), a peripheral processing unit ("PPU" 110) that communicates with the MPU and a peripheral control unit ("PCU" 112) capable of communicating with the PPU and with at least one associated peripheral device. The PCU has associated therewith a first number, m, of interrupts for signalling to the MPU. The MPU has a second number, n, of interrupt channels over which interrupts are communicable to said MPU. A first register (IN1616) is provided in the PCU for storing a routing value representing the assignment of the m interrupts of the PCU to a selected subset of m channels of the n interrupt channels. A second register (IN1222) is provided in the PPU for storing the routing value. A number, m, connections are provided between the PCU and the PPU for transmitting the m interrupts from the PCU to the PPU.
August 20, 1997
Date of Patent:
August 24, 1999
Texas Instruments Incorporated
John H. Cornish, Shannon A. Wichman, Qadeer A. Qureshi
Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.
Abstract: A novel addressing scheme for an RF-ID system or LAN network is presented in which an interrogator(reader) addresses a set of transponders, each transponder in this set having a common addressing scheme, and the addressed transponders respond only upon the matching of their own address with the received addressing scheme. The addressing scheme comprises a fixed size sub-address and a variable size mask. For example, assuming that the transponder address is 32 bits, the implementation of the addressing scheme can choose 4 bits for the size of the sub-address and 0, 4, 8, 12, 16, 20, 24, 28 bits for the size of the mask. By varying the addressing scheme according to the algorithm in FIG. 4, the reader will in time interrogate all the transponders individually, thus receiving their unique address and achieving the requested exhaustive inventory.
Abstract: The invention consists of attaching or embedding a "TIRIS" transponder (or other RF or IR or barcode or other identifying device) physically into the center of the proposed DVD disk. Within the memory of the transponder, both a predetermined address and a code word are preprogrammed into the transponder at the manufacturing level of the media product. The media player not only comprises functionality to play the disk, but also comprises the functionality to transmit an interrogation signal to the transponder, and then to receive the transponder response signal. Therefore, once a disk is input to a media player, the interrogation portion of the media player transmits an interrogation signal to the transponder located on the disk. Thus once empowered with the interrogation signal, the transponder accesses the predetermined address and the code word from it's memory.
Abstract: Circuits, systems and methods for operating a processor to process a plurality of sequentially arranged instructions. The method includes various steps, such as receiving (54) into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Next, determines (56) whether the received instruction comprises a memory access instruction. A memory access instruction is operable to access memory information of a specifiable size. In response to determining that the received instruction comprises a memory access instruction, the method generates (58) at least one micro-operation code corresponding to the memory access instruction and it also sets (60) a tag to the at least one micro-operation code, where the set tag requests a subsequent evaluation of the specifiable size. After the tag is set, the method later detects (64, 72) the set tag and, in response to the set tag, retrieves (66, 74) a current value of the specifiable size.
Abstract: A microprocessor (5) including a plurality of arithmetic logic units (42) is disclosed. At least one of the arithmetic logic units (42) includes a shifter circuit (50) for executing logical and arithmetic shift, rotate, and rotate-through-carry instructions in both the left and right directions, on data words of various lengths. The shifter (50) includes a series of input multiplexers (72, 74, 76, 78) for presenting the data word, carry bits, and extended sign bits to a first funnel shifter stage (80). Each of the multiplexers (72, 74, 76, 78) and first funnel shifter stage (80) are preferably realized by AND-OR-INVERT logic, to allow for 0 logic states and don't cares to be presented by the nonassertion of a control signal thereto. The shifter (50) is implemented as a right funnel shifter, with left shifts and rotates performed by presentation of the data word to the most significant bits of the first funnel shifter stage (80), followed by a right shift of the logical complement of the shift count.
Abstract: A computer system (6,7) includes first and second I/O circuits (932, 934, 51, 97), first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934, 51, 97), a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an interface between the notebook computer and the docking station to transfer DMA related information between the DMA controller and a requesting device in the docking station.
December 3, 1996
Date of Patent:
February 23, 1999
Texas Instruments Incorporated
James J. Walsh, Joseph Joe, Robert W. Milhaupt, James Bridgwater, Kazumi Haijima
Abstract: A lock (10) having inductive key detection includes a lock mechanism (14). A detector member (20) is movably disposed proximate the lock mechanism (14) such that the detector member (20) moves when a key engages the lock mechanism (14). The detector member (20) has a magnetic portion (24). An antenna (30) is disposed proximate the detector member (20) such that movement of the detector member (20) induces a signal in the antenna (30). A detector (42) is coupled to the antenna (30) and is operable to detect the signal in the antenna (30).
Abstract: An electronic system (6) has a power management logic circuit (920). A first power supply connector (1902) is electrically coupled to the power management logic circuit (920) and a second power supply connector (1904) is also electrically coupled to the power management logic circuit (920). The power management logic circuit (920) has a first logic section (920A) connected to the first power supply connector (1902), and the first logic section (920A) has a suspend output (SUSPEND#). A second logic section (920B) is connected to the second power supply connector (1904) for operation independent of the first logic section (920A) when power is available at the second power supply connector (1904, RTCPWR) and suspended at the first power supply connector (1902, VCC).
Abstract: A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (V.sub.DD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).
Abstract: An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5), and a terminal for a selectable supply voltage (VCCDK) and also has a power-good terminal (PWRGOOD5). A plurality of peripheral control circuits (910, 938, 932) are connected by an on-chip internal bus (904). The peripheral control circuits (910, 938, 932) connect to different ones of the internal on-chip supply conductors for operation on the first and second supply voltages (VCC3, VCC5), and the selectable supply voltage (VCCDK). Reset circuitry (2390) is provided for at least one of the peripheral control circuits. A control latch (PMU.sub.-- CNTRL) has a bit (VCCDRV5V) to which the reset circuitry (2390) is responsive.
Abstract: A single-chip integrated circuit device (110) includes an on-chip bus (904) and a plurality of integrated circuit functional blocks (934, 932) having respective clock inputs connected to the on-chip bus (904). An address decoder (in 1210) is provided responsive to particular addresses to supply an output of a differing character (IDE/NON-IDE) depending on whether or not the particular addresses are received. A clock generating circuit (1201) having a control input (IDE/NON-IDE) fed by the output of the address decoder (in 1210) and a clock output (SYSCLK) connected to the on-chip bus (904) supplies a clock signal that depends in rate on whether or not the particular addresses are received. Other circuits, systems, and methods are disclosed.
Abstract: A pipelined microprocessor (10) and system (2) incorporating the same, utilizing combined actual branch history and speculative branch history to predict branches, is disclosed. The microprocessor (10) includes a branch target buffer, or BTB, (56) having a plurality of entries (63) that are associated with previously branching instructions. Each entry (63) has a tag field (TAG) for storing an identifier for its branching instruction based upon the logical address therefore, and a target field (TARGET) for storing the target address for the branching instruction if the branch is taken. Each entry (63) also includes a branch history field (BH), the most-recent bits of which are applied to a pattern history table, or PHT, (53) as an index thereto to retrieve a prediction for the branch.
Abstract: A ring antenna (10) for resonant circuits for identifying metallic containers has an annular core (11) having at least one core surface (11a') corresponding to at least one surface of the container and made from ferrite. The core may be U-shaped, having a base portion and a first and second arm portions, or L-shaped, having a base portion and a first arm portion (11a). The antenna (10) also has a copper wire coil (12) wound around a first portion of the core; and an aluminum shield (13) affixed to the at least one core surface (11b') and separating the core from the surface of the container. Further, a interrogation system for identifying metallic containers includes the ring antenna (10) coupled to a resonant circuit (86) included in a transponder or a reader.