Abstract: An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.

Abstract: A system (5) and method are used for predicting and controlling the temperature of a semiconductor wafer (10) during a solder reflow process by controlling the operating profile of a solder reflow furnace (14). The emissivity of the surface of the wafer (10) is measured using an infrared device (11) prior to the solder reflow process. Using the measured emissivity value of the wafer (10), the peak temperature of the wafer (10) is predicted, and the operating profile of the solder reflow furnace (14) is adjusted accordingly to achieve a desired temperature profile of the wafer (10). A process for reflowing solder on a semiconductor wafer calculates a predicted peak temperature of a semiconductor wafer (10) and controls the actual temperature of the wafer (10) during a solder reflow process by controlling the operating profile of a solder reflow furnace (14).

Abstract: A frequency modulator (50, 150) for modulating a carrier signal according to a modulation data signal to provide a modulated output signal (RFout), comprises a reference signal generator (54, 154) coupled to receive the modulation data signal for performing a low frequency modulation process and for generating a reference signal modulated according to the modulation data signal, and a main synthesizer (52, 152) coupled to receive the modulated reference signal and the modulation data signal for performing a high frequency modulation process and for providing the modulated output signal at an output. Preferably, the modulated reference signal has a first modulation gain (Kr) and the modulated output signal has a modulation gain (KV) which is substantially proportional to the first modulation gain (Kr).

Abstract: A Micro-Electromechanical System (MEMS) switch (100) having a single, center hinge (120) which supports a membrane-type electrode (104) on a substrate (101). The single, center hinge (120) has a control electrode (104) coupled to the substrate (101) by an anchor (113), a hinge collar (121), a set of hinge arms (122, 123). The control electrode (104) has a shorting bar (106) coupled thereto and is electrically isolated from another control electrode (105), which is formed on the substrate (101). A travel stop (130) is positioned between the substrate and the control electrode (104). Another aspect of the present invention is a Single Pole, Double Throw (SPDT) switch (160) into which is incorporated the single, center hinge (170) and the travel stop (185, 186).

Abstract: A method of manufacturing a semiconductor device includes providing an apparatus (210, 510) having tabs (212, 214, 412, 414) for holding and separating semiconductor substrates wherein a first tab (212, 412) is different from a second tab (214, 414), using the first tab (212, 412) to support a semiconductor substrate (224) wherein the second tab (214, 414) does not support the semiconductor substrate (224), and exposing the semiconductor substrate (224) to a chemical to move the semiconductor substrate (224) towards the second tab (214, 414) without removing the semiconductor substrate (224) from the apparatus (210, 510).

Abstract: A portable electronic device including a display carrier detachably mounted to the portable electronic device. The display carrier including a plurality of display apparatus and an electronic display control. A data communication interface is provided between the display carrier and the portable electronic device for permitting data exchange between the plurality of display apparatus and the portable electronic device. The electronic display control, including a display management chip, controls the operation of the plurality of displays dependent upon the power source supplying power to the portable communication device.

Abstract: An input circuit (20) and a method for protecting the input circuit (20) from positive and negative overvoltages. The input circuit (20) includes an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (12), a P-channel MOSFET (13), a Zener diode (21), and a diode-connected transistor (22). The P-channel MOSFET (13) protects the N-channel MOSFET (12) from negative overvoltages. The Zener diode (21) and the diode-connected transistor (22) protect the N-channel MOSFET (12) from positive overvoltages. In addition, the Zener diode (21) protects the P-channel MOSFET (13) from positive overvoltages.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.

Abstract: A circuit (11) for tracking rapid changes in peak and trough voltages of a data signal includes a peak detector circuit (13) and a trough detector circuit (14) coupled to the input for detecting peaks and troughs in the data signal and providing a peak and trough detect output signals, respectively. A peak level rate of change detector (17) is coupled to the peak detector circuit (13) for detecting a rate of increase in the voltage level of detected peaks and to the trough detector circuit (14) for controlling the trough detector circuit to detect troughs when the voltage level of detected peaks rises rapidly. Similarly, a trough level rate of change detector (18) is coupled to the trough detector circuit (14) for detecting a rate of decrease in the voltage level of detected troughs and to the peak detector circuit (13) for controlling the peak detector circuit (13) to detect peaks when the voltage level of detected troughs falls rapidly.

Abstract: A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).

Abstract: An active bias compensation circuit (110) senses a quiescent current flowing in an amplifier (130) and adjusts the quiescent current to maintain an optimal DC biasing of the amplifier (130) over a wide range of factors, e.g., temperature variation, process variation, history of the amplifier (130), etc. The compensation circuit (110) includes two transistors (101, 102) forming a difference amplifier. A sensing voltage proportional to the quiescent current and a reference voltage are applied to the base electrodes of the two transistors (101, 102), which generates a bias signal in response to a difference between the sensing voltage and the reference voltage. The bias signal adjusts the quiescent current in the amplifier (130).

Abstract: An electronic assembly (10) includes a chip capacitor (11) having two major surfaces (12, 15) and a pair of electrodes (13, 14). A plurality of electrically conductive traces (20-23, 25-28) are formed on one (12) of the major surfaces. Some of the plurality of electrically conductive traces are electrically coupled to a first electrode (14) and some of the plurality of electrically conductive traces are coupled to a second electrode (14) of the pair of electrodes. Electronic circuit elements (16, 17, 18) are coupled to the plurality of electrically conductive traces (20-23, 25-28), thereby forming the electronic assembly (10).

Abstract: A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n-silicon to provide continuity at the interface.

Abstract: A sensor (100) includes a fixed gate field-effect transistor (138) that produces a quiescent signal (V.sub.QUIESC1) in a channel (336) when a control signal (V.sub.CONTROL) is applied to a source (332) of the FGFET. A movable gate field-effect transistor (MGFET) (108) produces a sense signal (V.sub.ACCEL) in a channel (316) in response to a physical condition of the sensor when the control signal is applied to a source (312) of the MGFET such that the sense signal is proportional to the quiescent signal. The difference between the currents in the FGFET and MGFET is amplified by a differential amplifier (230) to produce the output signal (V.sub.OUT) of the sensor. The difference between a reference signal (V.sub.RATIO) and the quiescent signal is amplified in an amplifier (206) to produce the control signal that adjusts the output signal to be proportional to the reference signal.

Abstract: A etcher (10) has an inner chamber (22) that is in communication with a collection chamber (17). A cover (33) is made from a substrate (11) and an outer housing (34). The cover (33) is attached to the etcher (10) so that the substrate (11) is suspended over the inner chamber (22). A recirculating system (29) is used to pass an etchant through a filter, into the inner chamber (22), across the substrate (11), into the collection chamber (17), and into a reservoir.

Abstract: A semiconductor component (10) includes a substrate (11), doped regions (15, 20) in the substrate (11), interconnect layers (23, 26, 29) coupled to one of the doped layers, and dielectric layers (21, 24, 27) between the interconnect layers (23, 26, 29) wherein a portion (48) of the top interconnect layer (29) overlies portions (47, 42, 43) of the underlying interconnect layers (23, 26) and wherein a portion (47) of the middle interconnect layer (26) does not overlie the portions (42, 43) of the bottom interconnect layer (23) and also does not overlie portions (32, 33) of one of the doped regions (20).

Abstract: A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.

Abstract: A semiconductor device includes a transistor (30, 51) having a gate electrode (15, 52) wherein the gate electrode (15, 52) has a highly resistive portion (24, 25, 55). The highly resistive portion (24, 25, 55) is integrated into the gate electrode (15, 52) and is coupled to the gate electrode (15, 52) using a via-less contact method.

Abstract: A semiconductor component includes a substrate (101), an electrode (105) located over the substrate (101), a heavily doped region (542) located in the substrate (101) and self-aligned to the electrode (105), an other heavily doped region (543) located in the substrate (101), a lightly doped region (422) located in the substrate (101) between the heavily doped regions (542, 543) and self-aligned to the electrode (105), and another lightly doped region (432) located in the substrate (101) between the lightly doped region (422) and the other heavily doped region (543).

Abstract: A sensor (10) is capable of detecting linear acceleration in the three Cartesian directions and the angular acceleration about three Cartesian axes. The sensor (10) has a conductive layer (32) that is free to move or rotate in any direction. A first, second, and third set of conductors are used to sense and quantify the acceleration of the conductive layer (32). The sensor (10) can also be operated as a closed loop system with the addition of a fourth set of conductors.