Abstract: An inspection system (20) has an image capture device (10) that is mounted onto a wafer prober (15) for the electrical verification of electronic components (60) having an emissive display (61). The image capture device (10) includes a lens (31) that collects the image generated by the emissive display (61). The image is passed to mirrors (36,37) which redirect a portion of the image into a pickup device (41). The emissive display (61) is partitioned into subregions (62-65) to facilitate the capturing of the image. As the image of each of the subregions (62-65) is collected by image capture device (10), the other subregions (62-65) are deactivated.

Abstract: A control circuit (100) which receives horizontal synchronising pulses (265) and generates a horizontal drive output signal (455) for a cathode ray tube (CRT) display. The horizontal control circuit (100) generates two ramp signals. A first ramp signal (410) for horizontal position adjustment of an image on the CRT display, and a second ramp signal (440) for propagation delay compensation of a deflection circuit (155) coupled to the CRT display. The control circuit (100) also provides digital of control of the duty cycle of the horizontal drive signal (455).

Abstract: In an electronic system (100), a regulator (200) couples a supply device (110) to a consuming device (120) through a series switch (210) and provides output current I.sub.OUT. A shunt switch (220) is provided across the output. Fast changes of I.sub.OUT due to switching on and off the consuming device (120) are accommodated by the regulator (200). The regulator (200) has a voltage divider (250, 260) to measure V.sub.OUT. Operational amplifiers (230 and 240') control transistors (210, 220) with different switching thresholds, They compare a measurement voltage V.sub.M derived from V.sub.OUT to a reference voltage V.sub.REF. When the consuming device (120) is switched off, the first amplifier (230) makes the series transistor (210) non-conductive; and then the second amplifier (240') makes the shunt transistor (220) conductive for a short time. Capacitance at the output node (205) is substantially discharged. After overshooting, the voltage V.sub.OUT returns to its previous value. Unwanted undershooting of V.

Abstract: An edge termination structure is created by forming trench structures (14) near a PN junction. The presence of the trench structures (14) extends a depletion region (13) between a doped region (12) and a body of semiconductor material or a semiconductor substrate (11) of the opposite conductivity type away from the doped region (12). This in turn forces junction breakdown to occur in the semiconductor bulk, leading to enhancement of the breakdown voltage of a semiconductor device (10). A surface of the trench structures (14) is covered with a conductive layer (16) which keeps the surface of the trench structures (14) at an equal voltage potential. This creates an equipotential surface across each of the trench structures (14) and forces the depletion region to extend laterally along the surface of semiconductor substrate (11).

Abstract: An electrically programmable memory comprising: a floating gate FET cell (10) having: a drain electrode, and a source electrode; means for applying to the drain electrode a first voltage (V.sub.PP) for a programming time (T.sub.P); means for applying to the source electrode a second voltage (V.sub.ML) for the programming time, the second voltage being variable between more than two levels so as to determine the quantity of charge induced on the floating gate and thereby to determine the multi-level value programmed into the cell substantially independently of the programming time. A multi-level value programmed into the cell is sensed by placing an iteratively or dynamically varying voltage on the source electrode, and current flow in the cell is sensed to determine the voltage on the floating gate.

Abstract: A power semiconductor device (10) and a method for increasing the turn-on time of the power semiconductor device (10). The power semiconductor device (10) has a first stage (13) and a second stage (14), where the transconductance of the first stage (13) is less than the transconductance of the second stage (14). The turn-on time of the power semiconductor device (10) is increased by turning on the first stage (13) before turning on the second stage (14).

Abstract: A semiconductor power device comprises a metal conductor (6) coupled to a semiconductor region (30) of the device, one or more bumps (8) formed in contact with the metal conductor (6) and a frame (14) formed of high conductivity material. The frame (14) comprises a connecting portion (18) for connecting to at least one of the one or more bumps (8) so as to provide an external connection to the semiconductor region (30) of the device.

Abstract: A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P.sup.+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P.sup.+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).

Abstract: A Magnetoresistive Random Access Memory (MRAM) device (10) and a method for manufacturing the MRAM device (10). The MRAM device (10) has a plurality of pairs of sense lines (21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B), a plurality of pairs of memory cells (51A, 51B), and a plurality of word lines (31, 32, 33, 34). For two adjacent sense lines (21A, 22A), a first end of the first sense line (21A) is placed adjacent to a second end of the second sense line (22A) and a second end of the first sense line (21A) is placed adjacent to a first end of the second sense line (22A). Decoding transistors (82, 83, 84, 85, 86, 87, 88, 89) are connected to the second ends of the plurality of pairs of sense lines (21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B).

Abstract: An optoelectronic connector (10) coupled to a fiber ferrule (38) containing an optical fiber (39) and a method for coupling the optoelectronic connector (10) to the fiber ferrule (38). The optoelectronic connector (10) has a base (11) and walls (13, 14, 17, and 18) that form a cavity (19). A semiconductor receiving area (26) extends into a first portion of the base (11) and an interconnect recess (27) extends into a second portion of the base (11). Alignment pins (31) extend from the second portion of the base (11). The optoelectronic connector (10) may be a unitary structure. The fiber ferrule (38) is inserted into the cavity (19) to form an optoelectronic device (30).

Abstract: A method and circuit (20) for reducing flicker. Pixel values (Y.sub.0, Y.sub.1, Y.sub.-1) are transmitted to input terminals (23, 21, 22) of the circuit (20). A first difference magnitude is calculated by subtracting the pixel value (Y.sub.0) of a middle pixel from the pixel value (Y.sub.-1) of an upper pixel and taking an absolute value of the result. A second pixel magnitude is calculated by subtracting the pixel value (Y.sub.0) of the middle pixel from the pixel value of a lower pixel and taking an absolute value of the result. A larger of the first and second pixel magnitudes is compared to a user-selected threshold value. The pixel value (Y.sub.0) of the middle pixel is either changed or left unchanged in accordance with the results of the comparison.

Abstract: A compact ROM array is formed in a single active region (5) bounded by field oxide regions, the array being formed of one or more ROM banks (6, 7). Each ROM bank has a plurality of pairs of N+ bit lines (1-1 to 4-2), a plurality of conductive word lines (15-1 to 16-2) formed on top of, and perpendicular to, the bit lines, and left-select (11) and right-select (12-1, 12-2) lines arranged parallel to the word lines to enable particular transistor cells in the array to be selected to be read. The transistor cells (40, 41) are formed by adjacent portions of adjacent bit lines together with the portion of the word line extending between them. Isolation regions (43) between the transistor cells are formed by implanting the substrate between them with Boron dopant of a low energy and concentration after the bit and word lines have been fabricated and the transistor cells are programmed by implanting a channel region (42) with Boron of a higher energy and concentration after the low energy implantation step.

Abstract: A semiconductor structure (10)includes a semiconductor substrate (12), a silicon layer (18)overlying the semiconductor substrate, a dielectric layer (16)overlying the silicon layer and having a contact opening to expose a portion of the silicon layer, and a metal layer stack (20)overlying the dielectric layer and having a portion in contact with the silicon layer through the contact opening. The metal layer stack comprises a barrier layer (24)of titanium with incorporated oxygen (of greater than about 11 atomic percent) to provide diffusion resistance against, for example, platinum, oxygen, and silicon.

Abstract: Ferroelectric transistors are combined with MOSFETs to perform logic functions. The logic functions include a non-volatile ferroelectric latch (30), a clocked non-volatile ferroelectric latch (50), a programmable switch (60), an edge-triggered complementary flip-flop (78), a tri-state logic circuit (80), a ferroelectric logic NAND-gate (100), a clocked ferroelectric logic NAND-gate (140), and a programmable logic function (150). The programmable logic function (150) includes a programming terminal (156) to select between a NOR-gate function and a NAND-gate function.

Abstract: A low-noise amplifier circuit (40) and a method for generating a bias voltage within the amplifier circuit (40). The amplifier circuit includes a cascode configured circuit (15) having a common emitter transistor (12) biased by a current sourcing circuit (43) and a common base transistor (13) biased by a bias voltage generator (21). The current sourcing circuit (43) measures a base current of the common emitter transistor (12) and transmits the base current to a current mirror (41). Further, a current source (50) transmits a bias current to the current mirror (41). The current mirror sums the currents from the current sourcing circuit (43) and the current mirror (41) and generates a mirror output current. A portion of the mirror output current drives the bias voltage generator (21) and a portion of the mirror output current serves as the base current of the common base transistor (13).

Abstract: A leadframe (1) includes a main frame having longitudinal outer rails (4) and a number of sub-frame (8) separated from the main frame by a slit (6) extending around at least part of the perimeter of the sub-frame (8). A plurality of flag portions (2), on which a semiconductor die is to be mounted, extend from the mainframe and a plurality of lead portions (12) extend from the sub-frame (8) towards the flag portions (2). The sub-frame (8) is bent twice in a zig-zag fashion so as to be in a plane parallel to that of the main frame so that the corresponding flag and lead portions overlap without affecting the dimensions of the outer edge portion of the main frame.

Abstract: A multiplier (10) includes a transconductor (14) and a multiplier core (34). The transconductor (14) converts an RF voltage signal to an RF current signal. The RF current signal modulates the quiescent currents flowing in current conducting elements (23, 24), thereby generating a modulated current signal. The modulated current signal is transmitted to the multiplier core (34), where it is combined with an LO signal to generate an output signal. The transconductor (14) and the multiplier core (34) have their current conduction paths separated from each other by the current conducting elements (23, 24).

Abstract: A first current (Iptat) having a magnitude proportional to absolute temperature is passed through a resistor (R3) and a PN-junction (QA) to produce first and second voltages (Vr+Vbe) having, respectively, positive and negative temperature coefficients which when summed provide a temperature stabilized internal reference voltage (Vbgrl). This internal reference voltage (Vbgrl) powers the current generator for currents (I1, 12)) which pass through a second resistor (R8, R9) and a second PN junction (Q20A, Q20B) to produce third and fourth voltages having respectively, positive and negative temperature coefficients which when summed provide a temperature stabilized external reference voltage (Vbgrl) having improved ripple rejection. There is no feedback from the external reference voltage (Vbgr2, V-out) to the first current (Iptat) generator (42).

Abstract: A battery protection system (20) controls a process for charging a battery pack (15). A hysteresis comparator (54) senses a charging current flowing through the battery pack (15) and switches off a charging switch (31) to interrupt the charging current when the charging current reaches an upper limit. A transient current is then generated by an inductor (34). The hysteresis comparator (54) senses the transient current flowing through the battery pack (15) and switches on the charging switch (31) to regenerate the charging current when the transient current decreases substantially to zero. Periodically, a battery monitoring circuit (40) switches off the charging switch (31) and measures an open circuit voltage across each battery cell in the battery pack (15). In response to the open circuit voltage of a battery cell reaching a fully charged voltage, the battery monitoring circuit (40) switches off the charging switch (31) to terminate the charging process.

Abstract: A method for forming a semiconductor sensor device comprises providing a substrate (4) and forming a sacrificial layer (18) over the substrate. The sacrificial layer (18) is then patterned and etched to leave a portion (19) on the substrate (4). A first isolation layer (6) is formed over the substrate (4) and portion (19) of the sacrificial layer and a conductive layer (12), which provides a heater for the sensor device, is formed over the first isolation layer (6). The portion (19) of the sacrificial layer is then selectively etched to form a cavity (10) between the first isolation layer (6) and the substrate (4), the cavity (10) providing thermal isolation between the heater and the substrate.