Patents Represented by Attorney, Agent or Law Firm Reza Mollaaghababa
  • Patent number: 6658579
    Abstract: The present invention provides a network device including redundant, synchronous central timing subsystems (CTSs) and local timing subsystems (LTSs) including control circuits for automatically selecting between reference signals from both central timing subsystems. Automatically selecting between reference timing signals allows each LTS to quickly switchover from a failing or failed reference timing signal to a good reference timing signal. Quick switchovers prevent data corruption errors that may result during slow switchovers where a failing or failed reference signal is used for a longer period of time prior to the switch over. In addition, since each LTS independently monitors its received reference timing signals, a problem on one reference timing signal is quickly detected by the LTS and the LTS switches over to the good reference timing signal regardless of whether any other LTSs detect a problem with their received reference timing signals.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: December 2, 2003
    Assignee: Equipe Communications Corporation
    Inventors: Colin Bell, Brian Branscomb, Mike A. Sluyski
  • Patent number: 6654903
    Abstract: The invention provides a method for fault isolation in a computer system, such as a network device. The method calls for providing a plurality of modular processes, and forming groups, based on hardware in the computer system, of one or more of the plurality of modular processes. A fault within a group is detected, and recovery from the detected fault is accomplished without affecting processes or hardware in other groups.
    Type: Grant
    Filed: May 20, 2000
    Date of Patent: November 25, 2003
    Assignee: Equipe Communications Corporation
    Inventors: Daniel J. Sullivan, Jr., Terrence S. Pearson, Barbara A. Fox, Joseph D. Kidder, Umesh Bhatt
  • Patent number: 6639910
    Abstract: The present invention provides a network device, such as a network switch or a router, having a high degree of modularity and reliability. The network device includes a data plane and a control plane. The data plane relays datagrams between a pair of receive and transmit network interface ports. The control plane runs management and control operations, such as routing and policing algorithms which provide the data plane with instructions on how to relay cell/packets/frames. Further, the control plane includes an internal control device that is primarily responsible for managing the internal resources of the network device, and a separate external control device that is primarily responsible for operations relating to the interfacing of the network device with an external environment.
    Type: Grant
    Filed: May 20, 2000
    Date of Patent: October 28, 2003
    Assignee: Equipe Communications Corporation
    Inventors: Roland T. Provencher, Brian Branscomb, Nicholas A. Langrind, Peter B. Everdell
  • Patent number: 6635559
    Abstract: The present invention provides methods and apparatus for creating insulating layers in Group III-V compound semiconductor structures having aluminum oxide with a substantially stoichiometric compositions. Such insulating layers find applications in a variety of semiconductor devices. For example, in one aspect, the invention provides vertical insulating layers separating two devices, such as photodiodes, formed on a semiconductor substrate from one another. In another aspect, the invention can provide such insulating layers as buried horizontal insulating layers of semiconductor devices.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: October 21, 2003
    Assignee: Spire Corporation
    Inventors: Anton C. Greenwald, Nader Montazernezam Kalkhoran
  • Patent number: 6605849
    Abstract: The present invention provides an analog frequency divider structure that receives an input signal at a selected frequency and generates an output signal at a fraction, e.g. one-half, of the input frequency. In one embodiment, the analog frequency divider structure is implemented as a MEMS device having a vibratory beam extending along a longitudinal axis between two fixed ends and a piezoelectric transducer coupled to the beam. The MEMS structure further includes a conductive layer disposed on at least a portion of the vibratory beam, which is capacitively coupled to a conductive electrode. A longitudinal excitation of the piezoelectric transducer can effect application of a periodic longitudinal deformation force to the vibratory beam. This deformation force causes the beam to vibrate in a transverse direction at its natural transverse vibrational frequency, which is selected to be a fraction of the input frequency.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: August 12, 2003
    Assignee: Symmetricom, Inc.
    Inventors: Robert Lutwak, William J. Riley, Jr., Kenneth D. Lyon
  • Patent number: 6602448
    Abstract: The present invention provides a method for forming a transparent optical element, such as an optical fiber, having a graded index of refraction. One preferred practice of the invention employs a hollow tube formed of an amorphous fluoropolymer and fills the tube with a liquid dopant material having an index of refraction that is different than that of the fluoropolymer. The heating of the filled tube for a sufficient duration causes the diffusion of the dopant material through the fluoropolymer, thereby producing a graded distribution of the dopant and hence a graded refractive index.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: August 5, 2003
    Assignee: GetronicsWang Co., LLC
    Inventor: Victor Ilyashenko
  • Patent number: 6593173
    Abstract: Methods of producing buried insulating layers in semiconductor substrates are disclosed whereby a dose of selected ions is implanted into a substrate to form a buried precursor layer below an upper layer of the substrate, followed by oxidation of the substrate in an atmosphere having a selected oxygen concentration to form an oxide surface layer. The oxidation is performed at a temperature and for a time duration such that the formation of the oxide layer causes the injection of a controlled number of atoms of the substrate from a region proximate to an interface between the newly formed oxide layer and the substrate into the upper regions of the substrate to reduce strain. A high temperature annealing step is then performed to produce the insulating layer within the precursor layer.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: July 15, 2003
    Assignee: Ibis Technology Corporation
    Inventors: Maria J. Anc, Robert P. Dolan
  • Patent number: 6468712
    Abstract: A radiation sensitive resin composition including a photo-acid generator and an aliphatic polymer having one or more electron withdrawing groups adjacent to or attached to a carbon atom bearing a protected hydroxyl group, wherein the protecting group is labile in the presence of in situ generated acid is described. The radiation sensitive resin composition can be used as a resist suitable for image transfer by plasma etching and enable one to obtain an etching image having high precision with high reproducibility with a high degree of resolution and selectivity.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: October 22, 2002
    Assignee: Massachusetts Institute of Technology
    Inventor: Theodore H. Fedynyshyn
  • Patent number: 6452195
    Abstract: A wafer holder assembly includes first and second main structural members from which first and second wafer-holding arms extend. The first arm is secured to the main structural members by a graphite distal retaining member. The second arm is pivotally biased to a wafer-hold position by a graphite bias member. This arrangement provides a conductive path from the wafer to the assembly for inhibiting electrical discharges from the wafer during the ion implantation process. The assembly can further include additional graphite retaining members for maintaining the structural integrity of the assembly during the extreme conditions associated with SIMOX wafer processing without the need for potentially wafer-contaminating adhesives and conventional fasteners. The wafer-contacting pins at the distal end of the arms can be formed from silicon. The silicon pins can be coated with titanium nitride to enhance electrical contact with the wafer and to provide an abrasion resistant surface.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: September 17, 2002
    Assignee: Ibis Technology Corporation
    Inventors: Theodore H. Smick, Robert S. Andrews, Bernhard F. Cordts, III
  • Patent number: 6423975
    Abstract: A wafer holder assembly includes first and second main structural members from which first and second wafer-holding arms extend. The first arm is secured to the main structural members by a graphite distal retaining member. The second arm is pivotally biased to a wafer-hold position by a graphite bias member. This arrangement provides a conductive path from the wafer to the assembly for inhibiting electrical discharges from the wafer during the ion implantation process. The assembly can further include additional graphite retaining members for maintaining the structural integrity of the assembly during the extreme conditions associated with SIMOX wafer processing without the need for potentially wafer-contaminating adhesives and conventional fasteners. The wafer-contacting pins at the distal end of the arms can be formed from silicon. The silicon pins can be coated with titanium nitride to enhance electrical contact with the wafer and to provide an abrasion resistant surface.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: July 23, 2002
    Assignee: Ibis Technology, Inc.
    Inventors: Theodore H. Smick, Geoffrey Ryding, Bernhard F. Cordts, III, Robert S. Andrews
  • Patent number: 6417078
    Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: July 9, 2002
    Assignee: Ibis Technology Corporation
    Inventors: Robert P. Dolan, Bernhardt F. Cordts, III, Maria J. Anc, Micahel L. Alles
  • Patent number: 6347851
    Abstract: Methods and compositions for forming polarizing images on an oriented substrate with specially formulated inks are disclosed. The inks can contain a dichroic dye, water, and a humectant. The dichroic inks are particularly advantageous when printed on specially coated molecularly oriented sheets through the technology of ink jet printing. The ink molecules align themselves parallel to the oriented molecules of the oriented sheet thereby forming a light-polarizing image.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: February 19, 2002
    Assignee: The Rowland Institute for Science
    Inventor: Julius J. Scarpetti
  • Patent number: 6332198
    Abstract: The present invention provides a method and apparatus for supporting multiple redundancy schemes in a single network device. In one network device, various redundancy schemes are supported including 1:1, 1+1, 1:N, no redundancy or a combination of redundancy schemes. In addition, the redundancy scheme or schemes for physical network device cards (i.e., universal port cards) or ports may be different from the redundancy scheme or schemes for forwarding network device cards. For example, a network manager may want to provide 1:1 or 1+1 redundancy for all universal port cards and/or ports but only 1:N redundancy for each N group of forwarding cards.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: December 18, 2001
    Assignee: Equipe Communications Corporation
    Inventors: Corey Simons, Terrence S. Pearson, Chris R. Noel, Joseph D. Kidder, Brian Branscomb, Nicholas A. Langrind, Daniel J. Sullivan, Barbara A. Fox
  • Patent number: 6324264
    Abstract: A method system, interface and server for establishing a communications call by selecting a B party (6) using an interactive device (16) connected to a public network (10,12), sending called address data for the B party (6) and calling address data for an A party (4) to a communications platform (18) of the public network (10,12), and establishing a call between the A and B parties (4,6) over the public network (10,12) using the communications platform (18) and the called and calling address data. The called address data can be accessed from the public network, and may reside on a server of a messaging network, such as the Internet.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: November 27, 2001
    Assignee: Telstra Corporation Limited
    Inventors: Victor Wiener, Calvin Jonathan Stein, Carlos Escobar
  • Patent number: 6248642
    Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: June 19, 2001
    Assignee: Ibis Technology Corporation
    Inventors: Robert Dolan, Bernhard Cordts, Marvin Farley, Geoffrey Ryding
  • Patent number: 6236168
    Abstract: An electronic circuit providing independent operation and application of instant start voltages to each of a plurality of lamps. In a first embodiment, a circuit includes inductively coupled first and second inductive elements disposed on a single bobbin. A capacitive element is coupled between the first and second inductive elements to allow the inductively coupled inductive elements to operate independently when a lamp is removed from the circuit. A steady state strike voltage is generated at the lamp terminals from which a lamp has been removed. In another embodiment, a circuit includes a first circuit path including a first inductive element coupled to a first lamp and a second circuit including a second inductive element coupled to a second lamp. The first and second inductive elements are inductively coupled to effectively cancel flux generated while the first and second lamps are energized.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: May 22, 2001
    Assignee: Electro-Mag International, Inc.
    Inventor: Mihail S. Moisin