Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size, including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.

Abstract: A polymeric infrared window (10) is described which comprises a sheet of polymeric material (14). Sheet 14 further may comprise a layer of molecular weave polymer material (34) fixed to a electromagnetic interference shield (32). In addition, a polymeric sheet (42) may be embossed with a binary defractive pattern (40) to create a polymeric defractive lens (38).

Abstract: A preferred embodiment of this invention comprises a perovskite-seed layer (e.g. calcium ruthenate 40) between a conductive oxide layer (e.g. ruthenium oxide 36) and a perovskite dielectric material (e.g. barium strontium titanate 42), wherein the perovskite-seed layer and the conductive oxide layer each comprise the same metal. The metal should be conductive in its metallic state and should remain conductive when partially or fully oxidized. Generally, the perovskite-seed layer has a perovskite or perovskite-like crystal structure and lattice parameters which are similar to the perovskite dielectric layer formed thereon. At a given deposition temperature, the crystal quality and other properties of the perovskite dielectric will generally be enhanced by depositing it on a surface having a similar crystal structure. Undesirable crystal structure formation will generally be minimized and lower processing temperatures may be used to deposit the perovskite dielectric layer.

Abstract: A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.

Abstract: In accordance with the present invention, there is provided a method by which narrow lateral dimensioned microelectronic structures can be formed using low temperature processes. An uncured resist layer (e.g. PMMA 42) is deposited on a supporting layer (e.g. silicon 40) and patterned. Then, by using an isotropic process such as a low temperature chemical vapor deposition, a conformal layer (e.g. silicon oxynitride 44) is deposited substantially evenly on the vertical walls and on the horizontal surfaces of the uncured resist layer. An anisotropic etch such as reactive ion etching is then used to substantially remove the conformal layer from the horizontal surfaces without substantially etching the conformal layer from the vertical walls of the resist. The resist can then be selectively removed, producing isolated vertical sidewall structures (e.g. silicon oxynitride 46) which could be used, for example, as a negative tone mask. Alternatively, instead of removing the resist, another resist layer (e.g.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate boron, which has been found to be substantially insoluble in BST, into a BST dielectric film 24. Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Boron included in a BST precursor may be used to form boron oxide in a second phase 30, which is distributed in boundary regions between BST crystals 28 in film 24. It is believed that the inclusion of boron allows for BST grains of a desired size to be formed at lower temperature, and also reduces the leakage current of the capacitive structure.

Abstract: A semiconductor device is disclosed which uses an embedded pillar 38 to prevent damage (e.g. dishing, smearing, overetching) to damascene conductors during fabrication, particularly where such conductors are relatively large. The device comprises an insulating layer 22 formed on a substrate 20 and having a substantially planar upper surface with a plurality of channels 26, 34 formed therein. Channel 34 may be described as comprised of contiguous narrow channel segments (including right segment 40, top segment 41, and left segment 42) enclosing pillar 38, which has a top surface substantially coplanar with the upper surface of layer 22. In one embodiment, pillar 38 is formed integrally as part of layer 22. In alternative embodiments, pillar 38 may be formed from an additional insulating or conducting layer.

Abstract: An electrostatic decontamination method and decontamination device (10) is disclosed for decontaminating the surface of a semiconductor substrate. The decontamination device (10) includes particle ionizing device (24) that charges contaminating particles (26) on the surface of semiconductor substrate (16) thereby creating ionized particles. Decontamination device (10) also includes substrate biasing device (12) for creating a charge accumulation layer (14) at the top of semiconductor substrate (16) so that the charge accumulation layer (14) has the same charge sign as the ionized particles. In addition, the invention analytically characterizes particles using contaminating particle isolator (44) which contains a particle ionizing device (24) that charges contaminating particles (26) on the surface of semiconductor substrate (16) thereby creating ionized particles.

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: An improved dielectric material and microcircuit having capacitive elements which employ such a dielectric material are disclosed. The dielectric material comprises polycrystalline barium strontium titanate doped with at least one donor element and having a grain size of less than 1 micron. In the preferred embodiments, the donor element may be Nb, Ta, Bi, Sb, Y, La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er or a combination thereof. The material may be further doped with an acceptor dopant to control resistivity. The microcircuit comprises capacitors having such a dielectric material and connected to a semiconductor substrate which contains embedded circuitry for reading the voltage across a capacitor.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A method and apparatus for removing particulate contaminants from a semiconductor wafer are disclosed. A wafer 10 is held in a wafer holder 12 at cleaning station 14. Cleaning station 14 has a rinse fluid supply system 18 which supplies, e.g. deionized water, to the wafer surface during particle removal. A cleaning pad 20 is mounted on a platen 22, substantially in the plane of wafer 10. Platen 22 is coupled to a drive mechanism 24, which may for example be an electric motor, and drive mechanism 24 is coupled to station 14 by an engagement mechanism 26 which provides vertical displacement to engage pad 20 and wafer 10 for particle removal, and also provides a controlled pad contact pressure during particle removal. In operation, rinse fluid from 18 is supplied to slowly rotating wafer 10, while pad 20 is rotated, preferably at 200 to 600 rpm, and contacted with wafer 10.

Abstract: A preferred embodiment of this invention is a hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, congelated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g AI 17).

Abstract: A stencil mask (10) has a membrane (14) under tensile stress and at least one pattern opening (22) formed through the membrane (14). A plurality of stress relief openings (30) are formed in the membrane for reducing stress-induced distortion of the membrane and the mask pattern. The stress relief openings (30) are positioned to relieve concentrations of stress within the membrane (14) such as those resulting from non-regularities within the pattern. In one embodiment, a screening material (56), less rigid than the membrane (14), is contained within the stress relief openings (30). Methods of forming such masks (10) are also disclosed.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for sample, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: Novel methods of forming capacitors containing high dielectric materials are disclosed. Capacitors are made by forming a layer of conductive metal nitride (e.g. ruthenium nitride, 28), then forming a layer of a high dielectric constant material (e.g. barium strontium titanate, 30) on the metal nitride layer, then forming a layer of a non-metal containing electrically conductive compound (e.g. ruthenium oxide, 32) on the layer of high dielectric constant material. Typically, the high dielectric constant material is a transition metal oxide, a titanate, a titanate doped with one or more rare earth elements, a titanate doped with one or more alkaline earth metals, or combinations thereof. Preferably, the conductive compound is ruthenium nitride, ruthenium dioxide, tin nitride, tin oxide, titanium nitride, titanium monoxide, or combinations thereof. The conductive compound may be doped to increase its electrical conductivity.

Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18, and dummy leads 16 proximate metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16 and thermoconductive insulating layer 22, which are both capable of dissipating the heat. A thin thermoconductive layer 24 may be deposited over the metal leads 14 prior to depositing at least the low-dielectric constant material 18 and the thermoconductive insulating layer 22. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.

Abstract: A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.