Abstract: Preferred embodiments include a microstrip patch antenna (38) which also acts as the resonator for an oscillator powered by IMPATT diodes (34, 36); this forms a monolithic transmitter (30) for microwave and millimeter wave frequencies.

Abstract: The invention described forms improved ferroelectric (or pyroelectric) layer by adding lead to an original perovskite layer having an original ferroelectric (or pyroelectric) critical grain size, then forming a layer of the lead enhanced perovskite layer having an average grain size less than the original ferroelectric (or pyroelectric) critical grain size whereby the remanent polarization (or pyroelectric figure of merit) of the layer is substantially greater than the remanent polarization (or pyroelectric figure of merit) of the original perovskite layer with an average grain size similar to the average grain size of the layer. The critical ferroelectric (or pyroelectric) grain size, as used herein, means the largest grain size such that the remanent polarization (or pyroelectric figure of merit) starts to rapidly decrease with decreasing grain sizes. Preferably, n-type lead enhanced perovskite layer is doped with one or more acceptor dopants whereby the resistivity is substantially increased.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti--A--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: Single crystal aluminum is deposited on SiGe structures to form metal interconnects. Generally, a method of forming single crystal aluminum on Si.sub.(1-x) Ge.sub.x is presented, including the steps of maintaining the substrate at certain temperature (e.g. between 300.degree. C. and 400.degree. C.) and pressure conditions (e.g. below 2.times.10.sup.-9 millibar) while aluminum atoms are deposited by a vacuum evaporation technique. This is apparently the first method of depositing single crystal aluminum on SiGe surfaces. Novel structures are made possible by the invention, including epitaxial layers 34 formed on single crystal aluminum 32 which has been deposited on SiGe 30. Among the advantages made possible by the methods presented are thermal stability and resistance to electromigration.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.

Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate organic dielectric materials to form self-aligned contacts (SACTs) reliably, even in deep, narrow gaps. In one embodiment, conductors 26 with insulating conductor caps 28 are formed over a silicon substrate 20 with a thin gate oxide 22. A conformal dielectric layer 30, preferably of thermally-grown oxide, is deposited over this structure, which is then covered with an organic-containing layer 32 and an inorganic cap layer 34 (e.g., CVD TEOS). An etch window 38 is patterned in photoresist layer 36 and used as a mask to etch cap window 39 through layer 34, using layer 32 as an etch stop. A second etch removes organic-containing layer 32 in contact window 41 (and preferably strips photoresist), using conformal layer 30 as an etch stop. A short anisotropic etch may be used to clear conformal layer 30 from gap bottom 43, after which conducting material 40 may be used to make electrical contact to the substrate.

Abstract: A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 32 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 24 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: An anisotropic liquid phase photochemical etch is performed by submersing a substrate 30 (e.g. copper) in a liquid 34 containing an etchant (e.g. hydrochloric acid) and a passivant (e.g. iodine), the passivant forming an insoluble passivation layer 36 (e.g. Cul) on the surface, preventing the etchant from etching the surface. The passivant and its concentration are chosen such that the passivation layer 36 has a solubility which is substantially increased when it is illuminated with radiation 38 (e.g. visible/ultraviolet light). Portions of the surface are then illuminated with radiation 38, whereby the passivation layer 36 is removed from those illuminated portions of the surface, allowing the etch to proceed there. Portions of the surface not illuminated are not etched, resulting in an anisotropic etch. Preferably, an etch mask 32 is used to create the unilluminated areas. This etch mask 32 may be formed on the surface or it may be interposed between the surface and the radiation source.

Abstract: A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42).

Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of holmium dopant (0.5 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size, including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without holmium precipitation than are observed for bulk BST. For holmium doping levels generally between 0.5 and 5% (compensated with titanium and/or manganese), better than 50% improvement in dielectric constant and two to six orders of magnitude reduction in leakage current (compared to undoped BST) have been observed for such films.

Abstract: A dry etch for metals such as copper using .pi.-acids in an energetic environment such as a plasma, laser, or afterglow reactor (102) or by using ligands forming volatiles at low temperature within a pulsed energetic environment.

Abstract: A thermal detection system (100, 200) includes a focal plane array (102, 202), a thermal isolation structure (104, 204) and an integrated circuit substrate (106, 206). The focal plane array (102, 202) includes thermal sensors (114, 214) formed from a pyroelectric element (116, 216), such as barium strontium titanate (BST). One side of the pyroelectric element (116, 216) is coupled to a contact pad (110, 210) disposed on the integrated circuit substrate (106, 206) through a mesa strip conductor (112, 212) of the thermal isolation structure (104, 204). The other side of the pyroelectric element (116, 216) is coupled to a common electrode (120, 220). In one embodiment, slots (128) are formed in the common electrode (120) intermediate the thermal sensors (114) to improve inter-pixel thermal isolation. In another embodiment, slots (236) are formed in the optical coating (224) to improve inter-pixel thermal isolation.

Abstract: A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have characteristics of implanted oxygen segregated into oxide layers.

Abstract: A mercury cadmium telluride (MCT) substrate 30 is immersed in a liquid 34 (e.g. 0.1 molar concentration hydrochloric acid) and illuminated with collimated radiation 24 (e.g. collimated visible/ultraviolet radiation) produced by a radiation source 20 (e.g. a 150 Watt mercury xenon arc lamp). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the MCT substrate 30. An etch mask 32 may be positioned between the radiation source 20 and the substrate 30. The MCT substrate 30 and liquid 34 may be maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the MCT is not appreciably etched by the liquid. Upon illumination the etch rate is substantially increased. A further aspect is the addition of a passivant (e.g. iodine) to the liquid which forms a substantially insoluble passivation layer 36 on the substrate which is removed or partially removed by the radiation 24.

Abstract: Semiconductor circuit provides an EEPROM programming charge pump (18), and includes a leakage current measuring device (12), a plurality of interconnected current mirrors, and a current controlled oscillator (16) for providing programming power to such EEPROM. The leakage current sensor (12) generates current nonlinearly related to device ambient temperature of the semiconductor circuit, the current mirrors combining and scaling the leakage current (14) with a constant current to provide a composite current altering frequency of the oscillator (16).

Abstract: This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substance 10, a buffer layer layer 12 over the substrate 10, and a channel layer 14 over the buffer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.