Abstract: A programmable resistive element is provided which includes a channel 16 comprising a layer of gallium arsenide. A programming barrier 18 is disposed outwardly from channel 16. A storage gate 20 comprising a layer of intrinsic gallium arsenide is disposed outwardly from programming barrier 18. An insulator 22, comprising a layer of aluminum-gallium-arsenide, is disposed outwardly from storage gate 20. A control gate 24 is disposed outwardly from insulator 22. First and second spaced apart contacts 26 and 28 contact channel 16.

Abstract: This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

Abstract: Photocapacitive detectors with varying bandgap Hg.sub.1-x Cd.sub.x Te (604) for two color detection and one color detection with increased potential well capacity. Preferred embodiments include a transparent insulated gate (608) on a top layer (632) of Hg.sub.0.8 Cd.sub.0.2 Te over a lower layer (634) of Hg.sub.0.83 Cd.sub.0.27 Te for detection of two infrared colors by varying gate potential to either confine the potential well to the top layer or to extend the potential well to both layers. Also, methods of compositionally grading the Hg.sub.1-x Cd.sub.x Te by fluid transport plus diffusion.

Abstract: A high speed signal driving scheme is disclosed which reduces timing delays associated with a signal line by limiting the voltage transition on the signal line from its precharged voltage.

Abstract: A transistor and a method of making a transistor are disclosed, where a tunnel diode is formed to make connection between the source of the transistor and the body node underlying the gate. For the example of an n-channel transistor, a p+ region is formed by implant and diffusion under the n+ source region, the p+ region in contact on one end with the relatively lightly doped p-type body node. The relatively high dopant concentration of both the p+ region and the n+ source region creates a tunnel diode. The tunnel diode conducts with very low forward voltages, which causes the body node region to be substantially biased to the potential of the source region. Methods for forming the transistor are also disclosed, including the use of a source/drain anneal prior to p-type implant, or alternatively a second sidewall oxide filament, to preclude the boron from counterdoping the LDD extension at the source side. Both silicon-on-insulator and bulk embodiments are disclosed.

Abstract: This is a method of forming a semiconductor-on-insulator wafer with a single-crystal semiconductor substrate.

Abstract: A coupling device (10) provides sealing members (24), (26), preferably Indium wire O-rings (72), (74), suitable for sealing engagement with an insulating member (28) under cryogenic, high-pressure conditions. Coupling device (10) is designed to couple a first metal pipe attached to a first adapter (12), and a second metal pipe attached to a second adapter (14), so that fluid may be conveyed via bore (36), chamber (84), and bore (48) under such cryogenic high-pressure conditions. According to the invention, the coupling device (10) provides effective sealing under these extreme conditions while also providing thermal and electrical insulation due to the advantageous construction featuring insulating member (28), first collar member (20) and second collar member (22).

Abstract: A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a buried perimeter (92) of the metal layer (62). A conductive lead (86) is formed in the Schottky via (68). A poly emitter terminal (46) connects a small sized emitter (50) formed in an epitaxial region (24) to the exterior. Poly emitter (46) presents a large area (76) to the exterior for alignment with a via (66) through a passivating dielectric layer (64), thus alleviating alignment problems.

Abstract: This is a p-n junction device and the device comprises: a substrate 10 composed of a semiconductor material; a heavily doped n type sub-collector layer 14 over the substrate; a n type collector layer 16 over the sub-collector layer; a heavily doped p type first base layer 18, over the collector layer; a p type second base layer 20, substantially thinner than the first base layer, over the first base layer, with the second base layer being less heavily doped than the first base layer; and a n type emitter layer 24 over the second base layer, whereby, the second base layer serves as a diffusion barrier between the base and the emitter. Other devices and methods are also disclosed.

Abstract: Methods, and products formed by such methods, of forming a self-aligned conductive pillar (16) on an interconnect (12) on a body (10) having semiconducting surfaces. A first mask (24) defines an inverse pattern for formation of an interconnect (12). The interconnect (12) is formed by additive metallization processes. A second mask (26) is formed over portions of the first mask (24) and the interconnect (12). Sidewalls of the first mask (24) which define at least one side of side of said interconnect (12) serve to also define at least one side of said conductive pillar (16). The second mask (26) also defines at least one side of the conductive pillar (16). The conductive pillar (16) is formed by additive metal deposition processes. The conductive pillar (16) is thus self-aligned to the interconnect (12) on which it is formed.

Abstract: A GaAs monolithic waveguide switch and system for low power consumption and high frequency switching wherein a single GaAs chip is flip-chip mounted onto a waveguide slot and inserted between interconnecting waveguides to provide single pole single throw switching. The GaAs chip includes an array of MESFETs along with connecting electrodes configured to provide low loss in the biased state and high loss in the unbiased state. The use of a single GaAs monolithic chip provides improved RF performance and manufacturability over discrete devices and provides lower power consumption as compared with silicon PIN diode waveguide switches.

Abstract: A method of forming an integrated-circuit device (10) which provides increased packing of unrelated conductors such as first gate (14) and second gate (16). Strap (20) electrically connects conductor contact area (28) to moat contact area (30) and yet also overlies and overlaps gate (16) above the overlap area (27) without any danger of shorting first gate (14) to second gate (16). According to the invention, the possibility of shorting strap (20) to second gate (16) and hence first gate (14) to second gate (16), is eliminated in the processing sequence wherein second insulating layer (24) is patterned to expose conductor contact area (28) at a prior step in the processing sequence. Subsequently, a third insulating layer (26) is formed to re-cover conductor contact area (28), yet the thickness of third insulating layer (26) is substantially less than the combination of the thickness of third insulating layer (26) and second insulating layer (24).

Abstract: An electron beam lithography method with multiple low-dose scans by an electron beam (320) exposes a resist (402) pattern.

Abstract: An on-chip transient event detector (FIG., 1) is fabricated onto an integrated circuit chip to provide rapid response to a detected event, such as a transient radiation dose or other condition that can cause transient current pulses. The transient event detector includes a detector circuit 10 that includes a narrow p-channel FET (12), and a wide n-channel FET (14). These detector transistors are coupled together and biased so that the narrow-channel transistor is normally on and the wide-channel transistor is normally off. A transient event, such as a photocurrent induced by radiation, causes a current pulse in the normally off wide-channel transistor that is sufficiently greater than the current in the narrow-channel transistor to cause a change in logic output, providing an event signal. The event signal can be used to disable memory WRITE operations during the transient event. The detector circuit can be integrated with an on-chip time-delay circuit (30) to provide a time-delayed system reset signal.

Abstract: A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50, 54) and in situ doped sidewall conductive filaments (66, 68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62, 64) to form diffused source regions (70, 72) of pass gate transistors (90) for each cell.

Abstract: A monolithically realizable radio frequency (RF) bias choke implemented as a parallel inductor/capacitor arrangement connected between a DC supply node and an RF circuit bias point.

Abstract: This invention is an SOI BICMOS process which uses oxygen implanted wafers as the starting substrate. The bipolar transistor is constructed in two stacked epitaxial layers on the surface of the oxygen implanted substrate. A buried collector is formed in the first epitaxial layer that is also used for the CMOS transistors. The buried collector minimizes the collector resistance. Selective epitaxial silicon is then grown over the first epitaxial layer and is used to form the tanks for the bipolar transistors. An oxide layer is formed over the base to serve as an insulator between the emitter poly and the extrinsic base, and also as an etch stop for the emitter etch. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the epitaxial layer and overlaps the oxide layer.

Abstract: This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropically etching the bonding layer forming chambers in the bonding layer; stacking the first and second wafers with the metal against the second wafer's bonding layer; forming a chemical bond between the metal layer and the bonding layer (e.g. between the titanium 20 and the poly 38) in a vacuum chamber, thereby creating micro-vacuum chambers (42) between the wafers; selectively etching the second wafer to form a thin semiconductor layer (e.g. epi layer 30). This is also a semiconductor-on-insulator wafer. The wafer comprises: a substrate (e.g. semiconductor substrate 20); a layer of metal (e.g. titanium 24) and semiconductor (e.g. silicide 40) over the substrate; a bonding layer (e.g.

Abstract: DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructure on top of an underlying CMOS address circuit. The CMOS chip surface contains several processing artifacts that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.

Abstract: A microwave oscillator circuit having an antenna, wherein the effective reactive impedance of the oscillator circuit is altered by the movement of a reactive impedance changing element past the antenna to cause change of the oscillation condition of the oscillator. A change in oscillation condition is sensed and sent to a utilization device to determine speed and/or position. The utilization device can be a computer which receives a signal from a wheel speed determining system, wherefrom a signal is sent back to a braking system for the wheel to control braking thereof. This can be accomplished individually for each of the four wheels to provide an anti-locking braking system.