Abstract: The use of trimethylarsine in place of tertiary butyl arsine for low pressure organometallic vapor phase epitaxy of GaAs:C to enhance the carbon doping efficiency of CCl.sub.4. The hole concentration is three times higher with trimethylarsine then with tertiary butyl arsine in the layer grown under similar conditions. As a result, higher growth temperatures can be used with trimethyl arsine, yielding more stable carbon doping. Annealing at 650.degree. C. for 5 minutes does not degrade the trimethyl arsine-grown layers while the tertiary butyl arsine-grown layer shows decreases in both hole concentration and mobility. Also a high level of hydrogen atoms is detected in tertiary butyl arsine-grown GaAs:C. The hydrogen level is about 30 times lower in the layers grown with trimethyl arsine. The reduced hydrogen concentration is an added advantage of using trimethyl arsine since hydrogen is known to neutralize acceptors in GaAs to reduce the carrier concentrations.

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).

Abstract: A metal oxide substrate (e.g. barium strontium titanate 34) is immersed in a liquid ambient (e.g. 12 molar concentration hydrochloric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury zenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the metal oxide substrate 34. An etch mask 32 may be positioned between the radiation source 20 and the substrate 34. The metal oxide substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the metal oxide is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.

Abstract: A titanate substrate (e.g. lead zirconate titanate 34) is immersed in a liquid ambient (e.g. 12 molar concentration hydrochloric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the titanate substrate 34. An etch mask 32 may be positioned between the radiation source 20 and the substrate 34. The titanate substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the titanate is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.

Abstract: A lateral resonant tunneling transistor is provided comprising heterojunction barriers (24) and a quantized region (33). Current between source contact (26) and drain contact (28) can be switched "ON" or "OFF" by placing an appropriate voltage on gate contacts (30) and (32). The potential on gate contacts (30) and (32) selectively modulate the quantum states within quantized region (33) so as to allow electrons to tunnel through heterojunction barrier (24) and quantized region (33). The method for fabricating comprises etching trenches through second barrier layer (20) and quantum layer (76) and regrowing a semiconductor to form heterojunction barrier (24).

Abstract: A process for forming a smooth conformal refractory metal film on an insulating layer having a via formed therein. This process provides extremely good planarity and step coverage when used to form contacts in semiconductor circuits and, in addition, offers improved wafer alignment capability as well as enhanced reliability which result from the smooth surface morphology. The process includes forming contact openings through an insulating layer to a semiconductor substrate; depositing a first blanket layer of titanium using deposition conditions that provide a conformal film that exhibits good step coverage at the contact opening; and forming a second blanket layer of titanium using deposition conditions that provide reduced surface asperity height. The process is ideally suited to forming an electrical interconnection system for semiconductor integrated circuit devices such as static or dynamic random access memories and is particularly useful in VLSI devices that incorporate multiple levels of interconnect.

Abstract: A method for making an adhesive ohmic contact to a p-type semiconductor metal substrate or layer (10) comprises tin and lead. The contact preferably includes a tin/lead film (24) approximately 2000 .ANG. in thickness. The p-type semiconductor compound contains mercury and, while described in conjunction with Hg.sub.1-x Cd.sub.x Te, other elements exhibiting group II and group VI chemical behavior and properties may be used A cap layer (30) is deposited over film (24), followed by insulating layer (32). Via (34) is then formed and, to complete contact (50), a metal (36) is deposited inside via (34).

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50, 54) and in situ doped sidewall conductive filaments (66, 68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62, 64) to form diffused source regions (70, 72) of pass gate transistors (90) for each cell.

Abstract: A method for forming a shallow junction (56) with a relatively thick metal silicide (52) thereover is provided. A first relatively thin layer (38) of a metal is deposited over the surface of a semiconductor substrate. An impurity (40) is then implanted (42) into or through the first layer (38). A relatively thick second layer (48) of metal is deposited over the first layer (38). An anneal process (50) is then performed to out-diffuse the impurities (40) from the first layer (38) into the substrate (32). The anneal also forms a combined metal silicide (52) from the first layer (38) and the second layer (48). The junction (56) thus formed has less surface damage, reduced spiking and reduced implant straggle than junctions formed according to the prior art. An alternate technique is also disclosed wherein an implant into or through a silicide layer is utilized.

Abstract: Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopant to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Abstract: A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anistropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

Abstract: This is a DMOS transistor and a method of forming a DMOS transistor structure. The method comprises: forming a polycrystalline silicon central gate region; forming a drain region in the substrate self-aligned to the central gate region; forming polycrystalline silicon gate sidewalls adjacent to the gate region; and forming a source region in the substrate self-aligned to the edges of the sidewalls. It can provide a channel region which is significantly longer (Ld) than it is in depth (essentially Lj) can be produced between the source region and the drain region, and thus the method provides an optimization of the transistor for lower on-resistance and thus a DMOS device having a MOS channel length longer than its parasitic JFET channel length. Preferably channel regions are formed which are 0.25-0.75 um in depth and the channel regions have an Ld of 1.0-2.5 um.

Abstract: A niobium pentoxide substrate 34 immersed in a liquid ambient (e.g. 10% hydrofluoric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the Nb.sub.2 O.sub.5 substrate 34. An etch mask (e.g. organic photoresist 32) may be positioned between the radiation source 20 and the substrate 34. The Nb.sub.2 O.sub.5 substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the Nb.sub.2 O.sub.5 is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.

Abstract: Disclosed is a process for forming a bipolar transistor at the face (22) of a semiconductor layer. A refractory metal layer (34) is deposited on the face (22) to cover a base area (38) thereof. A dopant (40) is implanted through the metal layer (34) within the base area (38) to penetrate the face (22). The metal layer (34) is then removed from the face within an emitter area (48) contained within the base area (38). A dopant is then diffused into the face within the emitter area (48). Finally, the dopants are annealed to form a shallow base region (66) that spaces an emitter region (64) from a collector region (12, 14). The process of the invention can form a high-concentration emitter/base junction only 400 Angstroms from the surface of the semiconductor layer.

Abstract: A package receives and encapsulates an optoelectronic integrated circuit chip. A plurality of optically transmissive filaments have first ends coupled with the chip and second ends opposite the first ends positioned outside the package. In a preferred embodiment, the first ends are flamed off to form spherical lenses, which are then used to contact optically active devices on the integrated circuit chip.

Abstract: A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total thickness less than 250 .ANG.. A doped third semiconductor layer formed over the second layer. The net has a dopant concentration in the second layer is greater than the net dopant concentration in the third layer. A gate layer is positioned over the third layer. In a preferred embodiment the second layer is a pulse-doped pseudomorphic material.There is also provided a method for making the heterostructure field effect transistor. A doped pseudomorphic semiconductor layer of a first conductivity type is formed between first and second other semiconductor layers, the second layer including a net dopant concentration of the first conductivity type. A Schottky gate electrode is formed in contact with the second layer.

Abstract: The invention relates to a method of scribing and separating dice from each other after fabrication in a semiconductor wafer in a manner such that active circuit regions in the dice reside as near to an edge of a die as possible. The wafer is anistropically etched through the active layer and into the substrate through an opening in the mask to form a generally V-shaped channel with the dice then being separated along a vertex of the channel. The dice are then positioned to abut each other in the form of a mosaic.

Abstract: This is a method of forming a semiconductor integrated circuit with isolation regions, (possibly wide and narrow) comprising of a thin oxide film and deposited anisotropic oxide. It uses an inorganic layer (e.g. noncrystalline silicon) to mask what will be active areas and allows for the growth of a thermal oxide film in the trenches reducing the parasitic channel formation along the trenches. The use of anisotropic oxide to fill the trenches allows for wide and narrow trenches to be simultaneously filled to the desired depth. The removing of inorganic layer and the use of anisotropic oxide to fill the trenches produces a flat planar surface and finer isolation regions.

Abstract: A method of passivation of Hg.sub.1-x Cd.sub.x Te and similar semiconductors by surface oxidation (such as anodic) followed by chemical conversion of the oxide to either sulfide or selenide or a combination of both is disclosed. Preferred embodiments provide sulfide conversion by immersion of the oxide coated Hg.sub.1-x Cd.sub.x Te in a sodium sulfide solution in water with optional ethylene glycol and the selenidization by immersion in a solution of sodium selenide plus sodium hydroxide in water and ethylene glycol. Also, infrared detectors incorporating such sulfide and selenide passivated Hg.sub.1-x Cd.sub.x Te are disclosed.