Abstract: An AGC circuit (12) contains a programmable gain stage comprising an operational amplifier (150) and one or more capacitor arrays (101, 121) for controlling the closed loop gain of the operational amplifier. The output signal (V.sub.O) of this operational amplifier is rectified, and the rectified signal is alternately integrated with a reference voltage (V.sub.ref) of opposite polarity to the rectified AGC signal. The polarity of the integrated voltages operates a counter stage (200). The output bits (0.sub.2 -0.sub.N) of the counter are used to control switches (134-2 through 134-N, 135-2 through 135-N, 110-2 through 110-N, 111-2 through 111-N) in the one or more capacitor arrays which control the closed loop gain of the operational amplifier of the AGC circuit of this invention.

Abstract: A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (V.sub.error) is inverted and integrated one time for each integration of the input voltage (V.sub.in), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (V.sub.out).

Abstract: A unique dynamic operational amplifier is constructed utilizing a switched capacitor (25) as the biasing means, wherein the switched capacitor biasing means is capable of effectively doubling the power supply voltage supplied to the dynamic operational amplifier, thus greatly extending the range of the input voltage (V.sub.IN) and output voltage (V.sub.OUT) of the dynamic operational amplifier.

Abstract: A digital to analog converter (100) utilizes a current mirror connected to a reference voltage (V.sub.REF) to generate a constant reference current (I.sub.REF). A voltage divider (R.sub.1 and R.sub.2) is used in conjunction with a plurality of MOS transistors (X.sub.1 -X.sub.N) serving as current mirrors having specific current carrying capabilities which are controlled by selected binary digits (bits) of a digital signal. By the appropriate connection of desired ones of said plurality of MOS transistors, a specific fraction of said reference current is caused to flow through said plurality of MOS transistors. The amount of current flowing through said plurality of MOS transistors generates an output voltage (V.sub.OUT) from the digital to analog converter of this invention. This output voltage may be positive or negative with respect to the reference voltage, thus the output voltage is bipolar.

Abstract: A semiconductor memory device (100) utilizing a programming transistor (54) capable of switching high programming currents, and a read transistor (53) capable of sensing the state of the cell (i.e. programmed or unprogrammed). The programming transistor, utilized only when programming the cell, being rather large, is rather slow. The read transistor, utilized only when reading the cell, is constructed to be as small as possible, thereby achieving a substantially increased reading speed over prior art PROM devices which utilize a single transistor per memory cell for both programming and reading.

Abstract: This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit results in a significant reduction in space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This reduction in size results in a significant reduction in the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns.

Abstract: A recording head for use in an electrostatic printer comprises four staggered rows of styli. Signals for driving each row of styli are transmitted through a buffer wherein the signals for the first row of styli are transmitted without delay to the styli, the signals for the second row of styli are transmitted with an appropriate delay of a first selected time, the signals for the third row of styli are transmitted with an appropriate delay of a second selected time and the signals for the fourth row of styli are transmitted with an appropriate delay of a third selected time. The delay means comprises a random access memory driven by address counters controlled by a control sequencer to function as a delay. The four staggered rows of styli are formed by a novel method wherein the styli in the second row are formed between the styli in the first row and the stylis in the third and fourth rows are formed by making use of the grooves formed between the styli in the first and second rows.

Abstract: A recording head for use in an electrostatic printer comprises four staggered rows of styli formed by a novel method wherein the styli in the second row are formed between the styli in the first row and the styli in the third and fourth rows are formed by making use of the grooves formed between the styli in the first and second rows. By forming the rows of styli on a cylindrical drum, two recording heads are obtained from each fabrication run wherein the recording head in one set of styli is the mirror image of the recording head in the other set of styli. Should an error occur in the manufacture of the styli by placing the third row of styli in the grooves where the fourth row of styli normally belongs, the resulting recording heads are identical to those obtained with the proper placement of the third and fourth rows with the exception that the position on the drum of each type of recording head is reversed.

Abstract: A memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivity type. Second, third and fourth regions of first conductivity type are then formed in the first region, said second and third regions being separated by a first portion of the first region and said third and fourth regions being separated by a second portion of the first region. A fifth region of first conductivity type is then formed in the second portion of the first region and a first electrode is attached to the fifth region. This electrode is electrically isolated from the second, third and fourth regions and extends on insulation over the first portion of said first region to said second region and also extends over said third region and a part of the second portion of said first region. This electrode is covered by insulation.

Abstract: The floating gate in an N channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain.

Abstract: A semiconductor READ ONLY MEMORY (ROM) device is constructed by using a series of word lines as a mask during the fabrication of the underlying bit lines. The width of the word lines over each memory cell determines the characteristics of that cell (i.e. programmed or unprogrammed).

Abstract: A memory device is constructed having a plurality of output ports, each output port being one word wide, such that a plurality of words may be accessed from the memory simultaneously.

Abstract: This invention significantly reduces the problem of undesired lateral diffusion of P type dopants into the P type active area. A thin oxide/nitride sandwich is formed on the surface of a semiconductor wafer and patterned to serve as a mask defining the to-be-formed active areas. An N type dopant implant is performed on the surface of the wafer to establish the desired field inversion threshold voltage. The wafer is then oxidized, with the oxide/nitride sandwich preventing oxide growth in the active areas. A layer of photoresist is applied to the wafer and patterned to expose the to-be-formed P well. That portion of the oxide exposed by the photoresist is removed, as is that portion of the substrate within the to-be-formed P well which contains N type dopants. P type impurities are then applied to the wafer. The photoresist is then removed and the P type dopants are diffused with little oxide growth to provide a P well having the desired dopant profile.

Abstract: An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal (.phi..sub.D, .phi..sub.D) in a unique manner, thereby eliminating the effects of spurious error voltages (E.sub.S) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch. A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFET switch.

Abstract: The invention is relating to a press for compressing a powdery material to grains comprising a loosely arranged, rotatable annular, perforated mould supported and guided by a rotatable mould holder and by an axially displaceable supporting member which supports the mould at the end remote from the mould holder, the side face of a mould engaging the mould holder being urged by the supporting member with a given force against the mould holder in the operational position of the press in a manner such that during the operation of the press the mould is caught along by the mould holder owing to the force produced between the mould holder and the mould, whilst a rotatable roller is arranged in the mould whereby an uninterrupted channel is provided at least at the level of the side face of the mould engaging the drivable mould holder.

Abstract: A support member is used to mount a heat motor and at least one electrical resistance heating element for actuating said heat motor. The support member is made of a thermally conductive material with cylindrical openings which receive the motor and heating element(s). Heat from the resistance element actuates the motor by heat conductance through the support.

Abstract: In accordance with this invention, a dynamic RAM cell comprises a substrate of one conductivity type in which is formed a first region of a second and opposite conductivity type and a first pocket of this second conductivity type. The first pocket has formed therein a second pocket of the same conductivity type as the substrate but of a higher doping concentration than the substrate. By forming a channel between the first region and the first pocket, the charge in this first pocket can be controlled to represent a selected bit of information. The magnitude of charge stored in this first pocket can then be determined by forming a channel across this first pocket to the second pocket from the substrate. The time rate of change of the potential in the second pocket then is representative of the stored charge of information in the first pocket due to the fact that the impedance of the channel formed across the first pocket is directly related to the amount of charge stored in the first pocket.

Abstract: An integrator circuit utilizing an operational amplifier (19) and switched capacitor elements (11, 13 and 16) in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage (V.sub.OUT) free from the effects of voltage offsets inherent in operational amplifiers.

Abstract: In an analog to digital converter circuit for a CODEC a single reference voltage is used for comparing both positive and negative input signals. The circuit comprises a capacitor array to define the decision levels corresponding to the end points of companding elements with the top plates of all capacitors in the array being connected in parallel through a single switch from an incoming analog signal source and to one input of a comparator. The bottom plate of each capacitor is connected to one of a series of three-way switches, all of which have separate terminals connected to the output of a voltage reference, to separate switches on a linear resistor string connected to the voltage reference output, and to ground. All switches are controlled by control logic connected to the comparator output.