Abstract: A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translates vector instructions in the lowered IR to vector instructions from the non-standard instruction set. The vector instructions from the non-standard instruction set are defined such that assembly language programs written with them do not suffer from the effects of pipeline delays. Therefore, according to the present invention, the code generator eliminates the effects of pipeline delays when transforming the lowered IR to the assembly language program. Since the code generator eliminates the effects of pipeline delay, the scheduler's task is greatly simplified since the scheduler need only maximize the use of the functional units.

Abstract: A monolithic processing chip for a parallel processing system comprises a processor circuit and a memory circuit. The processor circuit processes data received from said associated memory circuit in accordance with processor control signals to generate processed data. The memory circuit includes a plurality of registers for storing data, each register including at least one data storage cell including at least one dynamic memory data bit store for storing a data bit. The memory circuit is responsive to memory control signals and register address signals to transmit stored data from the registers to the processor for processing and to store processed data received from the processor circuit in the register identified by the register address signals.

Abstract: A digital computer comprising a plurality of message generating nodes interconnected by a routing network. The routing network transfers messages among the message generating elements in accordance with address information identifying a destination message generating element. Each message generating node includes a message data generator and a network interface. The message data generator generates message data items each including an address data portion comprising a destination identifier. The network interface includes a message generator and an address translation table, the table including a plurality of entries identifying, for at least one destination identifier, a translated destination identifier. The message generator, in response to the receipt of a message data item from the message data generator, generates a message for transmission to the routing network.

Abstract: An optimizer for optimizing an intermediate representation (IR) tree having multiple nodes. The IR tree represents a partial compilation of a source code. The source code is written using a high level language supporting data parallel processing. According to the present invention, the optimizer optimizes the IR tree by minimizing the number and size of temporary parallel variables in the IR tree. Such minimization optimizes the IR tree because temporary parallel variables require an enormous amount of space in memory.

Abstract: A system processes directed graphs, each directed graph comprising a plurality of nodes interconnected by arrows defining a relationship among the nodes, each node defining a selected attribute. The system comprises an initial population means, a subsequent generation population generating means, and a competition simulation means. The initial population means provides an initial population of directed graphs that comprises an initial current generation during an initial iteration. The subsequent generation population generating means generates, in response to selected ones of the directed graphs in each of a plurality of current generations, modified directed graphs for use generation during a subsequent iteration.

Abstract: Apparatus is described for allocating the resources of a parallel computer. The computer is divided into a plurality of processor arrays, a plurality of host computers are provided, and the host computers and the arrays are interfaced by an interconnection means that can connect any host computer to any one or more of the arrays. A specific connection means comprises a plurality of first multiplexers, one for each array, for writing data from any host computer to any array; a plurality of second multiplexers, one for each host computer, for reading from any array to any host computer; and control means for controlling the multiplexers so as to connect the host computers and arrays as desired by the users. The control means comprises a status register which specifies the connections between the host computers and the processor arrays as specified by the users.

Abstract: A massively parallel computer system including a plurality of processing nodes under control of a system controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises at least one processor, a memory, and a router node connected to the communications links for transferring in a series of message transfer cycles messages over the communications links. The controller enables each processing node to establish a message queue in its memory. The controller further enables storage of messages received by the processing nodes for their respective processors during a message transfer cycle to be stored in the message queue.

Abstract: A massively parallel computer arrangement and method for processing seismic data, comprising signal amplitude as received by a plurality of receivers each for a plurality of shots, to generate a profile of subterranean formations. Initially, the arrangement, iteratively for a plurality of subsets of the shot data referred to as "shot chunks," converts, the signal amplitude data into frequency component amplitude data identifying the amplitudes of the frequency components of the signal data. After that is done for all of the shot chunks, the arrangement iteratively processes the amplitude data for successive frequency chunks to generate a profile, during each iteration iteratively generating profile information for successive subterranean layers and processing the frequency component amplitude data to downward-migrate the receiver and shot data to facilitate generating profile information for the next layer.

Abstract: A method and apparatus are described for improving the utilization of a parallel computer by allocating the resources of the parallel computer among a large number of users. A parallel computer is subdivided among a large number of users to meet the requirements of a multiplicity of databases and programs that are run simultaneously on the computer. This is accomplished by device(s) for dividing the parallel computer into a plurality of processor arrays, each of which can be used independently of the others. This division is made dynamically in the sense that the division can readily be altered and indeed in a time sharing environment may be altered between two successive time slots of the frame. Further, the parallel computer is organized so as to permit the simulation of additional parallel processors by each physical processor in the array and to provide for communication among the simulated parallel processors. Device(s) are also provided for storing virtual processors in virtual memory.

Abstract: A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion.

Abstract: A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data. The control node generates processing requests for transfer to selected ones of the processing nodes as identified by associated request address information, and receives processed data in response, the request address information identifying selected ones of the processing nodes to receive a processing request in parallel. The request distribution network distributes the processing requests to the processing nodes and returns processed data to the control node. The network includes a plurality of request distribution nodes connected in a plurality of levels to form a tree-structure, including an upper root level and a lower leaf level.

Abstract: A method and apparatus are disclosed for aligning a plurality of multi-processors. The apparatus preferably comprises an alignment unit associated with each processor and a logic network for combining the output of the alignment unit and for broadcasting information to these units. Alignment is achieved by inserting in the instruction stream from each processor that is to be aligned a request for alignment, by testing for prior completion of any instructions that must be completed and by causing all processors to wait until they have all made the request for alignment and completed necessary prior instructions. The alignment unit associated with each processor monitors the instruction stream to detect a request for alignment. The logic network illustratively is an array of AND gates that tests each alignment unit to determine if it has detected a request for alignment. When all the units have made such a request, the logic network informs the alignment units; and the alignment units inform the processors.

Abstract: A processing element array and a controller. The processing element array comprises a plurality of processing element nodes interconnected by a plurality of communications links in the form of a hypercube. Each processing element node has a memory including a plurality of storage locations for storing data, and in addition has a hypercube address. The controller controls the processing element nodes in parallel to enable the transfer of data items in a selected manner among the storage locations of the processing element nodes in a series of communications steps. The controller generates a base communications table and enables the processing element nodes to, in parallel, generate respective processing element node communications schedule tables as a selected function of the base communications table and the respective node's hypercube address.

Abstract: A query processing system for processing queries in connection with a document text base which has entries each identifying a document and a word in the document. The query processing system includes a plurality of processing elements for processing data in response to commands, and a control arrangement for controlling the processing elements in parallel. The control arrangement first enables the processing elements to generate a segmented posting file having entries, at least some of which have a word identifier and a document identifier. The entries form an array all of whose entries with the same document identifier are contained within one column. The rows of the segmented posting file are aggregated into segments each having a selected number of rows with each segment containing entries having word identifiers within an identified word identifier range.

Abstract: A computer comprising a plurality of processing elements and an input/output processor interconnected by a routing network. The routing network transfers messages between the processing elements and the input/output processor. The processing elements perform processing operations in connection with data received from the input/output processor in messages transferred over the routing network and transferring processed data to the input/output processor in messages over the routing network, the processing elements being connected as a first selected series of leaf nodes. The input/output processor includes a plurality of input/output buffers connected as a second selected series of leaf nodes of the routing network for generating messages for transfer over the routing network to a series of processing elements forming at least a selected subset of the processing elements during an input/output operation.

Abstract: A digital computer having a plurality of message generating elements each generating and receiving messages and a network for transferring messages among the message generating elements. The network includes a plurality of node clusters interconnected in a tree pattern from a lower leaf level to an upper root level, each node cluster including at least one node group with node clusters in a level above at least one predetermined level having a larger number of node groups than node clusters of the predetermined level for transferring messages among the message generating elements.

Abstract: A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation.