Abstract: A mass storage system for connection to a computer. The mass storage system includes a plurality of independently-controllable storage modules, each storage module having a storage element for storing data in a plurality of storage locations and a retrieval arrangement for retrieving data from selected ones of the storage locations. A word assembly arrangement receives data from the storage modules in parallel and generates in response thereto data words for transfer to the computer system. A system control module selectively enables the retrieval arrangements of the storage modules to retrieve in parallel data from corresponding storage locations of all of the storage elements, or to retrieve data from diverse locations in selected storage modules.

Abstract: A data coupling arrangement for successively receiving, in parallel, nibbles of respective data words, each nibble having a value, and for selectively coupling nibbles associated with one word in response to the relative values of the words. The selective coupling is determined by an identifier indication. The identifier indication is generated in response to a selected relationship between values represented by the nibbles from the respective words, until after nibbles are received whose values differ. At that point, the identifier indication is maintained in its condition thereby enabling the transfer of nibbles subsequently received from the same data word.

Abstract: A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal.

Abstract: A power supply system for powering a plurality of loads. The system includes a plurality of energizeable power supply circuits each associated with one of the loads for supplying power thereto in response to a power supply circuit control signal. An actuable power sharing arrangement is connected to all of the power supply circuits to facilitate sharing of power among the power supply circuits in response to a power sharing control signal. In addition, a control circuit generates the power supply control signals to individually controlling energization of each of the power supply circuits and the power sharing control signal to maintain the power sharing arrangement in an actuated condition when the power supply circuit control signals are controlling all of the power supply circuits to be energized, and otherwise maintaining the power sharing arrangement in a de-actuated condition.

Abstract: A memory controller and a method for controlling a memory including at least one memory bank including a plurality of storage locations. The memory controller receives memory access requests over a bus in a digital computer system and, in response initiates a memory access operation in connection with a storage location. The memory controller comprises a memory access control circuit that receives memory access requests over the bus and for performing a memory access operation in connection with a storage location in response thereto. A memory refresh control circuit includes a yellow refresh control circuit and a red refresh control circuit, both of which control refresh of the memory bank(s). The yellow refresh control circuit initiates a refresh operation in connection with a memory bank while the memory access control circuit is performing a memory access operation.

Abstract: A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor, generates messages, each including an address defining a path through the interconnection network from the source processor to one or more of the processors which are to receive the message as destination processors. The interconnection network establishes, in response to a message from the source processor, a path in accordance with the address from the source processor in a downstream direction to the destination processors thereby to facilitate transfer of the message to the destination processors. Each destination processor generates response indicia in response to a message. The interconnection network receives the response indicia from the destination processor(s) and generates, in response, consolidated response indicia which it transfers in an upstream direction to the source processor.

Abstract: A data transfer arrangement for use in a data processing system comprising a processing array and at least one input/output unit and a host for issuing commands, including data transfer commands, to both the processing array and the input/output unit. The processing array and input/output unit include interfaces are interconnected by a bus and comprise an information transfer means, a control transfer means including a cycle identifier transfer means, and a transfer control means. The information transfer means transmits and receives information signals, including arbitration, target select and data signals, over information transfer lines of the bus. The cycle identifier transfer means transmits and receives cycle identifier signals over cycle identifier lines of the bus. The transfer control means is connected to the information transfer means and the control transfer means and enables a data transfer in a plurality of phases, including an arbitration phase, a selection phase and a data transfer phase.

Abstract: Classification of natural language data wherein the natural language data has an open-ended range of possible values or the data values do not have a relative order. A training database stores training records, wherein each training record includes predictor data fields. Each predictor data field containes a feature, wherein each feature is a natural language term, and a target data field containing a target value representing a classification of the record. Features may also include conjunctions of natural language terms and each feature may also be a member of a category subset of features. The training database stores, for each feature, a probability weight value representing the probability that a record will have the target value contained in the target data field if a feature contained in a corresponding predictor data field occurs in the record.

Abstract: A massively parallel processing system comprising a plurality of processing nodes controlled in parallel by a controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises a memory, a transposer module and a router node. The memory stores data in slice format. The transposer module is connected to the memory and generates transpose data words of selected ones of the data slices from the memory. The router node is connected to the transposer module and to the communications links and transfers transpose data words over the communications links to thereby transfer the data slices between processing nodes. Finally, the controller controls the memories, transposer modules and router nodes of the processing nodes in parallel, to facilitate transfer of data slices among the processing nodes in unison.

Abstract: A system for generating communication pattern information for facilitating communication among processing nodes interconnected over communications links in a predetermined pattern to form a massively parallel processor. The system includes a mapping element and a communication pattern information generating element. The mapping element maps problem vertices from a problem graph onto processing nodes of a massively-parallel processor in relation to a communication cost function representing delays associated with communicating among processing nodes to which the respective problem vertices have been mapped. The communication pattern information generating element generates communication pattern information in connection with problem vertices mapped onto processing nodes, for use in directing message transfers among processing nodes to facilitate transfers of messages among the processing nodes over the communications links as defined by the problem graph.

Abstract: A verification system for verifying authorized use of a credit or bank card or other identification card. The verification system makes use of an image embossed on or laminated onto a card, and information stored on a magnetic strip or other storage arrangement laminated onto or otherwise affixed to the card. The information stored on the card is related to the image embossed on the card. A card reader reads the image and generates a information defining the image. In addition, the card reader reads the information and compares it to the image signature to determine if they conform. Further use of the card may be based on the degree of comparison between the information read from the card and the image signature.

Abstract: A method and apparatus are disclosed for aligning a plurality of multi-processors. The apparatus preferably comprises an alignment unit associated with each processor and a logic network for combining the output of the alignment unit and for broadcasting information to these units. Alignment is achieved by inserting in the instruction stream from each processor that is to be aligned a request for alignment, by testing for prior completion of any instructions that must be completed and by causing all processors to wait until they have all made the request for alignment and completed necessary prior instructions. The alignment unit associated with each processor monitors the instruction stream to detect a request for alignment. The logic network illustratively is an array of AND gates that tests each alignment unit to determine if it has detected a request for alignment. When all the units have made such a request, the logic network informs the alignment units; and the alignment units inform the processors.

Abstract: A parallel processor array is disclosed comprising an array of processor/memories and devices for interconnecting these processor/memories in an n-dimensional pattern having at least 2.sup.n nodes through which data may be routed from any processor/memory in the array to any other processor/memory. Each processor/memory comprises a read/write memory and a processor for producing an output depending at least in part on data read from the read/write memory and on instruction information. The interconnecting device comprises devices for generating an addressed message packet that is routed from one processor/memory to another in accordance with address information in the message packet and a synchronized routing circuit at each node in the n-dimensional pattern for routing message packets in accordance with the address information in the packets.

Abstract: A digital to analog conversion system includes two digital to analog converters, a selector circuit and a control circuit. Each digital to analog converter generates an output signal having a voltage level which can be varied in response to a control signal. The selector circuit is connected to the digital to analog converters for selectively coupling as a system output signal the output signal from one of the digital to analog converters in response to a selection signal.

Abstract: A storage system for data words in which error correction bits are generated for each data word and are stored independently from the data word on a separate mechanically-driven medium. In another aspect, the storage system serves a wide high throughput parallel bus by storing different portions of each data word that appears on the bus in different asynchronous storage units.

Abstract: An interest rate scenario generation system generates a plurality of paths through a binomial lattice arrangement to facilitate generation of a like plurality of interest rate scenarios. The system includes a plurality of processing elements each for performing processing operations, communications links for enabling each of the processing elements to transmit data with at least one other processing element, and a control arrangement. The configuration control element logically establishes the processing elements in a plurality of rows and columns, each row being associated with a path through the binomial lattice used in generating an interest rate scenario, and successive columns being associated with successive steps through the binomial lattice arrangement. The configuration control element configures the rows to enable the processing elements to communicate with one other processing element in the respective row.

Abstract: A parallel computer comprised of a plurality of identical processors, each processor having control and data inputs and outputs for communication with the host computers and separate interprocessor inputs and outputs for communication between the processors. The processors are permanently interconnected through interprocessor communications routers into a first, single n-cube array for purposes of interprocessor communication. The data and control inputs and outputs of the processors are separately connected in parallel to the host computers through a resource allocation means to divide the first, single n-cube array of processors into a multiplicity of smaller second arrays controlled by selected ones of the host computers.

Abstract: A chip array comprising a plurality of integrated circuit chips. Each chip comprises a plurality of processors, each processor including a data generation circuit for generating data and data receiving circuit for receiving data, a plurality of on-chip links for interconnecting the processors on each chip to form a processor array on the chip to facilitate the parallel transfer of data generated by the processors along selected directions in the processor array during a parallel data transfer operation, and a plurality of sets of selectively-energizable data transfer terminals. Each set of the data transfer terminals facilitates the transfer of data transmitted by processors along an edge of the processor array defined on the chip, between chips along a selected direction in the chip array during the parallel data transfer operation, with at least one set of data transfer terminals facilitating the transfer of data along at least two non-collinear directions in the chip array.

Abstract: A router comprising a plurality of routing nodes interconnected by a plurality of communications links in a multi-dimensional pattern for transferring messages, each message including an address including a series of address digits each associated with one of the series of dimensions. Each router node includes a switch circuit for selectively coupling messages, received from a communications link associated with a dimension, over a communications link associated with a dimension in accordance with the address. The switch circuit includes a series of message coupling circuits each associated with a dimension, each message coupling circuit being connected to receive messages from a communications link associated with a preceding dimension and to transmit messages over the communications link of the associated dimension, each message coupling circuit further being connected to the message coupling circuits of proximate dimensions.

Abstract: A parallel processor is disclosed which combines the advantages of an array of bit-serial processors and an array of word-oriented processors. Further, the invention provides for ready communication between data organized in bit-serial fashion and that organized in parallel. The processor comprises a plurality of word-oriented processors, at least one transposer associated with each processor, said transposer having n bit-serial inputs and m bit parallel outputs and a bit-serial processor associated with each bit-serial input of the transposer. The parallel processor further comprises a memory for each bit-serial processor and a data bus interconnecting the memory, the bit-serial processors and the bit-serial inputs of the transposer. The transposer converts serial inputs to parallel, word organized outputs which are provided as inputs to the word-oriented processors.