Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.

Abstract: A base station apparatus is provided. The base station apparatus includes an orthogonal frequency division multiplexed (OFDM) encoder and a time division multiplexer. The OFDM encoder is configured to encode a plurality of data streams into a corresponding plurality of OFDM tones, where one of the corresponding plurality of OFDM tones includes an OFDM preamble tone that indicates a mapping of remaining OFDM tones within the plurality of OFDM tones to one or more of a plurality of mobile stations, and indicates at least one of the plurality of tones addressed to a particular mobile device, and wherein the preamble tone is not fixed to the selected particular mobile device through communication. multiplexes a plurality of streams over a forward link channel for receipt by the plurality of mobile stations, where the corresponding plurality of OFDM tones are encoded as one of the plurality of streams.

Abstract: A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.

Abstract: An access node wirelessly coupled to a plurality of access terminals, having a subband scheduler, a plurality of orthogonal frequency division multiplex elements, and a plurality of antennas. The subband scheduler receives precoded data, and schedules transmission of a preamble signal and a plurality of data streams. The plurality of orthogonal frequency division multiplex elements converts the preamble signal and the plurality of data streams into a corresponding preamble tone and a corresponding plurality of data tones. The preamble tone indicates a mapping of the plurality of data tones to one or more of the plurality of access terminals. The plurality of antennas transmits the corresponding preamble tone and the corresponding plurality of data tones in timely fashion for receipt by the plurality of access terminals. The corresponding preamble tone and the corresponding data tones are transmitted over subbands of a code division multiple access (CDMA)-based carrier frequency.

Abstract: An optical USB device includes an electro-optical converter configured to receive optical signals from an optical fiber and to convert them into first electrical signals and configured to receive second electrical signals and to convert them into optical signals for transmission to the optical fiber. A USB 3.0 pin-compatible connector is coupled to the electro-optical converter. The pin-compatible connector is configured for coupling to a USB 3.0 connector of another USB device. The pin-compatible connector includes a first pair of pins configured for transmitting the first electrical signals from the optical USB device. The pin-compatible connector also includes a second pair of pins configured for receiving the second electrical signals into the optical USB device. The pin-compatible connector also includes a third pair of pins configured for transceiving third electrical signals according to a non-USB serial bus interface protocol to control and configure the electro-optical converter.

Abstract: A method for providing improved reverse link transmission timing in an access terminal is provided. The method includes processing automatic repeat request (ARQ) bits from a MAC bit processing unit for a previous sub-frame. The ARQ bits comprise a hybrid ARQ (H-ARQ) bit, a last ARQ (L-ARQ) bit, and a packet ARQ (P-ARQ) bit. The method also includes calculating the maximum allowed reverse rate and grant size for a MAC flow. The method further includes distributing grants to each application in the MAC flow. The method also includes storing a stored read pointer in an application transmit queue, for each application in the MAC flow. The method also includes preparing data for transmission, in response to storing the stored read pointer for each application in the MAC flow, based on the ARQ bits. The method also includes transmitting the data.

Abstract: A method for performing a hash operation, including providing an atomic hash instruction that directs a microprocessor to perform a the hash operation and to indicate whether the hash operation has been interrupted by an interrupting event; translating the atomic hash instruction into first and second micro instructions; via a hash unit, first executing the first micro instructions to accomplish the hash operation according to the hash mode; and via an integer unit, second executing the second micro instructions in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation. The atomic hash instruction has an opcode field, configured to prescribe the hash operation, and a hash mode field, configured to prescribe that the microprocessor accomplish the hash operation according to a one of a plurality of hash modes.

Abstract: Extending acknowledgement messages from two states to at least three states is described, whereby such messages constitute a packet quality indication (PQI) reflecting quality or usability of the received signal. In an HARQ system, a transmitting station can flexibly select a better alternative for the next information to transmit on the basis of such PQI. One aspect includes determining how best to correct an unsuccessful packet transmission based on quality information about the specific packet. Implementing apparatus and procedures are described.

Abstract: An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The machine specific register is configured to store a value therein. The access controller is coupled to the feature fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the feature fuse is blown, and is configured to direct the JTAG control chain to enable the precluded extended JTAG operations if the value matches an override value within the access controller during a period that the value is stored within the machine specific register.

Abstract: A multi-core bus termination apparatus includes a location array and a plurality of drivers. The location array generates a plurality of location signals that indicate locations on the bus of a corresponding plurality of nodes that are coupled to the bus, where the locations comprise either an internal location or a bus end location. Each of the plurality of drivers has one of the corresponding plurality of nodes, and controls how the one of the corresponding plurality of nodes is driven responsive to a state of a corresponding one of the plurality of location signals. Each of the plurality of drivers has configurable multi-core logic. The configurable multi-core logic enables pull-up logic and first pull-down logic if the state indicates the bus end location. The configurable multi-core logic disables the pull-up logic and to enable the first pull-down logic and second pull-down logic if the state indicates the internal location.

Abstract: An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D? pins of the USB 3.0 connector whether a device plugged into the USB 3.0 connector is a conventional USB 3.0 device or an optical USB device, where the optical USB device employs one of the D+ and D? pins of the USB 3.0 connector to transmit a data signal and the other to transmit a clock signal.

Abstract: Automatic provisioning of an access point base station or femtocell. The method may include the femtocell transmitting first information (e.g., location information, signal measurement information, capability information, etc.) to a service provider (e.g., over an IP network). The femtocell may receive second information from the service provider, where the second information includes one or more operational parameters. The operational parameters may include hand-off parameters, admission policy information, PN or scrambling codes, power parameters, and/or other parameters. The femtocell may operate according to the received parameters to provide access for a plurality of access terminals in a local area.

Abstract: Time synchronization of an access point base station. The method may include receiving an assignment message from a service provider comprising a plurality of parameters. The plurality of parameters may include an access point base station frequency assignment, a network identifier, an access point base station identifier, a neighbor list, a PN offset, and/or a scrambling code. The access point base station may then synchronize with the macro base station. Synchronizing may include searching for a strongest macro base station in the neighbor list, synchronizing a long code of the access point base station to the macro base station, estimating a propagation delay between the macro base station and the access point base station, and initializing a state of the access point base station PN code using the propagation delay to provide system time synchronization.

Abstract: System and method for managing connections in a mobile device. A first application may be executing on the mobile device. A first application request, including first quality of service (QOS) parameters and first connection information for the first application, may be received. The first QOS parameters and the first connection information may be stored in a routing table. A first connection for the first application may be established based on the first QOS parameters and the first connection information. A second application may be executing on the mobile device. A second application request, including second QOS parameters and second connection information for the second application, may be received. The second QOS parameters and the second connection information may be stored in the routing table. A second connection for the second application may be established based on the second QOS parameters and the second connection information.

Abstract: System and method for wirelessly communicating between a base station and a mobile device. The base station wirelessly sends a first one or more overhead messages to the mobile device. The first one or more overhead messages may include at least one parameter. The mobile device may wirelessly receive the first one or more overhead messages from the base station, including the at least one parameter. The base station may wirelessly send a second one or more messages to the mobile device according to a schedule based on the at least one parameter. The mobile device may wirelessly receive the second one or more messages according to the schedule based on the at least one parameter. The mobile device may schedule a sleep cycle based on the at least one parameter, which may reduce battery consumption in the mobile device. The second one or more messages may be sent less frequently than the first one or more overhead messages.

Abstract: An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor is a single integrated circuit disposed on a single die, and executes non-secure application programs and a secure application program. The secure application program is executed in a secure execution mode. The non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-volatile enabled indicator register that is configured indicate whether the microprocessor is within the secure execution mode or a non-secure execution mode, where contents of the non-volatile enabled indicator register persist through power removal and reapplication to the microprocessor.

Abstract: Provided is automatic gain control (AGC) in which a feedback filter has a parameter that is changed based on information regarding data-packet boundaries. In one representative embodiment, the bandwidth of the filter temporarily is increased, or the time constant of the AGC filter temporarily is decreased, within a vicinity of each actual or potential packet boundary.

Abstract: A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit disposed within execution logic, executing the one of the hash operations. The executing includes first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

Abstract: A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.