Abstract: A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.

Abstract: A microprocessor apparatus and method are provided, for selectively controlling write back of condition codes. The microprocessor apparatus has translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction includes an extended prefix and an extended prefix tag. The extended prefix disables write back of the condition codes, where the condition codes correspond to a result of a prescribed operation. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and generates the result, and disables write back of the condition codes.

Abstract: An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.

Abstract: A method enabling I/O devices to be shared among multiple operating system domains, including first communicating with each of the operating system domains according to a protocol that provides exclusively for a single system domain ithin the load-store fabric; and second communicating with the shared I/O endpoint according to a variant of the protocol to enable the shared I/O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains. The second communicating includes encapsulating an OS domain header within a transaction layer packet that otherwise comports with the protocol, wherein the value of the OS domain header designates the corresponding one of the operating system domains; and via core logic within a swithching apparatus, mapping the independent operating system domains to the shared I/O endpoint.

Abstract: An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external instruction bus, and translates each of the macro instructions into associated native instructions for execution. If a first form of a first macro instruction is retrieved, the instruction translation logic directs the microprocessor to enable a native bypass mode and indicates such by asserting a first bit within a control register. The bypass logic is coupled to the instruction translation logic.

Abstract: A conditional execution apparatus in a microprocessor is provided. The conditional execution apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies a condition, where execution of an operation prescribed by the extended instruction depends upon realization of the condition. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for the microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and evaluates the condition. If the condition is not realized, then the extended execution logic precludes execution of the operation.

Abstract: An apparatus and method are provided to offload TCP/IP-related processing, where a server is connected to a plurality of clients, and the plurality of clients is accessed via a TCP/IP network. TCP/IP connections between the plurality of clients and the server are accelerated. The apparatus includes an accelerated connection processor and a target channel adapter. The accelerated connection processor bridges TCP/IP transactions between the plurality of clients and the server, where the accelerated connection processor accelerates the TCP/IP connections by prescribing remote direct memory access operations to retrieve/provide transaction data from/to the server. The target channel adapter is coupled to the accelerated connection processor. The target channel adapter executes the remote direct memory access operations to retrieve/provide the transaction data. The TCP/IP transactions are accelerated by offloading TCP/IP processing otherwise performed by the server to retrieve/provide transaction data.

Abstract: A TCP-aware target adapter for accelerating TCP/IP connections between clients and servers, where the servers are interconnected over an Infiniband™ fabric and the clients are interconnected over a TCP/IP-based network. The TCP-aware target adapter includes an accelerated connection processor and a target channel adapter. The accelerated connection processor bridges TCP/IP transactions between the clients and the servers. The accelerated connection processor accelerates the TCP/IP connections prescribing Infiniband remote direct memory access operations to retrieve/provide transaction data from/to the servers. The target channel adapter is coupled to the accelerated connection processor. The target channel adapter supports Infiniband operations with the servers, including execution of the remote direct memory access operations to retrieve/provide the transaction data.

Abstract: Apparatus and method for determining an optimum promotion plan for merchandising of products for sale. A scenario/results processor enables a user to prescribe an optimization scenario, and presents the optimum promotion plan to the user, where the optimum promotion plan is determined by execution of the optimization scenario. The demand engine models relationships between potential prices of the products and market demand for the products, where the potential prices correspond to potential promotion events and potential supplier offers. The activity based cost engine estimates demand chain costs for the products based upon the market demand. The promotion optimization engine employs the market demand and the demand chain costs to determine the optimum promotion plan, where the optimum promotion plan maximizes a merchandising performance figure of merit according to the optimization scenario, and where the optimum promotion plan comprises a subset of the promotion events and potential supplier offers.

Abstract: A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor includes an apparatus, for providing a fallback far jump-call speculative target address that corresponds to a current far jump-call branch instruction. The microprocessor apparatus includes a far jump-call branch target buffer and a fallback speculative target address generator. The far jump-call branch target buffer stores a plurality of code segment bases and offsets corresponding to a plurality of previously executed far jump-call branch instructions, and determines if a hit for the current far jump-call branch instruction is contained therein. The fallback speculative target address generator is coupled to the far jump-call branch target buffer.

Abstract: A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first block of cache lines in an exclusive state and to copy the contents of a second block of cache lines into the first block of cache lines. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first block of cache lines in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second block of cache lines into the first block of cache lines.

Abstract: An apparatus and method for performing early correction of a conditional branch instruction in a pipeline microprocessor is disclosed. Early branch correction logic examines early status flags to detect a branch misprediction. The early status flags are generated in response to an instruction preceding the branch instruction earlier in the pipeline than the architected status flags are generated and may or may not be valid. If the early status flags are valid and indicate a misprediction, the early correction logic corrects the misprediction. If the pipeline stages below the early correction logic stage become void of uncompleted flag-modifying instructions, such as after a pipeline flush, the early status flags are re-validated by copying to the architected status flags to the early status flags. Late branch correction logic corrects the misprediction if the architected status flags indicate a misprediction and if the early correction logic did not correct the misprediction.

Abstract: An apparatus and method for generating early status flags in a pipeline microprocessor is disclosed. The apparatus includes early status flag generation logic that receives an instruction, an early result of the instruction, and a valid indicator of the early result and responsively generates the early flags. If the instruction is flag-modifying, then the early status flags are stored in an early flags register. The early flags in the register are invalidated if the early result from which they are generated is invalid. The early status flags and associated valid indicator may be employed by subsequent conditional instructions for early execution to avoid delay in waiting for the architected status flag values to be generated by execution units later in the pipeline. The early flags are revalidated if all flags-modifying instructions in pipeline stages below the early flag generation logic, if any, have already updated the architected status flags.

Abstract: A method for providing interface to an apparatus for optimizing a promotion plan for merchandising products, including utilizing a computer-based scenario/results processor within an optimization server to present a sequence of data entry templates to a user, whereby the user specifies an optimization scenario, the optimization server optimizing the promotion plan according to modeled market for the products and calculated demand chain costs for the products, where the calculated demand chain costs include fixed and variable costs for the products; and generating a plurality of optimization results templates and proving these templates to the user, wherein optimum promotion events and optimum supplier offers are presented.

Abstract: A technique for determining optimum prices of products. The apparatus includes a scenario/results processor, a demand engine, an activity based cost engine, and a price optimization engine. The scenario/results processor enables a user to prescribe an optimization scenario, and presents the optimum prices to the user, where the optimum prices are determined by execution of the optimization scenario. The demand engine models relationships between potential prices of the products and market demand for the products. The activity based cost engine estimates costs for the products based upon market demand. The price optimization engine employs the market demand and the demand chain costs to determine the optimum prices, where the optimum prices are a subset of the potential prices, and where the optimum prices maximize a merchandising performance figure of merit according to the optimization scenario.

Abstract: A microprocessor apparatus for exclusive prefetch and initialization of cache lines, including translation logic and execution logic. The translation logic translates a block allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to prefetch and initialize a block of cache lines. The block allocate and initialize instruction is encoded to direct the microprocessor to prefetch and initialize the block of cache lines. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the block of cache lines in the exclusive state. Upon receipt, the execution logic initializes the block of cache lines to the specified value. The allocation and initialization of the specified number of cache lines occurs in parallel with execution of other instructions in a program flow of an application program.

Abstract: A microprocessor apparatus for exclusive prefetch of a block of data from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended block prefetch instruction into a micro instruction sequence directing a microprocessor to prefetch a specified number of cache lines, where the extended block prefetch instruction is encoded to direct the microprocessor to prefetch the specified number of cache lines in the exclusive state. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the specified number of cache lines in the exclusive state, where the specified number of cache lines includes data entities that are to be subsequently modified, and where prefetching the specified numbers of cache lines in the exclusive state occurs parallel with execution of program instructions prior to execution of subsequent store instructions that direct the microprocessor to modify the data entities.

Abstract: A microprocessor apparatus that enables exclusive prefetch of a cache line from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended prefetch instruction into a micro instruction sequence that directs a microprocessor to prefetch a cache line in an exclusive state, where the extended prefetch instruction is encoded to direct the microprocessor to prefetch the cache line in the exclusive state. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues a transaction over a memory bus that requests the cache line in the exclusive state, where the cache line comprises a data entity that is to be subsequently modified, and where prefetching the cache line in the exclusive state occurs in parallel with execution of program instructions prior to execution of a subsequent store instruction that directs the microprocessor to modify the data entity.

Abstract: A microprocessor apparatus for exclusive prefetch and initialization of a cache line from memory, including translation logic and execution logic. The translation logic translates an allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to prefetch a cache line in an exclusive state and to initialize the cache line to a specified value, where the allocate and initialize instruction is encoded to direct the microprocessor to prefetch the cache line in the exclusive state and to initialize the cache line to the specified value. The execution logic receives the micro instruction sequence, and issues a transaction over a memory bus that requests the cache line in the exclusive state. Upon receipt, the execution logic initializes the cache line to the specified value. The allocation and initialization of the cache line occurs in parallel with execution of other instructions in a program flow of an application program.

Abstract: A method and apparatus are provided for writing to a flags register in a pipeline microprocessor. Responsive to a macro instruction that directs a write to the flags register, a mask is generated using destination information for the write and privilege level information for the write, where the mask permits updates of particular bits within the flags register that are appropriate for the current operating mode. The mask is then ANDed with new values for bits within the flags register and the result is written to the flags register in a single instruction cycle.