Abstract: Laser diode with independent electronic and optical confinement, referred to as decoupled confinement, comprising an active region, i.e. an active layer, a single quantum well layer or a multi-quantum well layer, embedded in a carrier confinement structure providing for an energy barrier at least on one side of the active region. This energy barrier reduces carrier leakage out of the active region. The carrier confinement structure is embedded in an optical confinement structure which guides the optical light wave. The inventive laser diode is characterized in that the height of the energy barrier confining the carriers, and the refractive index step providing for optical waveguiding of the light wave are decoupled.

Abstract: A hulling optical bridge includes light means for supplying light and splitter means for splitting the light into a first light beam and a second light beam. The first light beam is directed to a surface having a parameter to be measured, and a first photodetector receives light reflected from or transmitted through the surface and generates a first signal indicative of the magnitude of the reflected or transmitted light. A second photodetector receives the second light beam and generates a second signal indicative of the magnitude of the second light beam. An electronic balancing circuit operates in a first mode when the parameter is maintained at a constant level, for adjusting the first and second signals to equal magnitudes, and operates in a second mode when the parameter varies, for applying a compensating signal to the first signal to balance the first and second signals.

Abstract: A conductive line is applied to a substrate by aligning the conductive line in juxtaposition with a selected area of the substrate; bonding the conductive line to the substrate; and detaching the conductive line from a carrier in which the conductive line is suspended. The carrier has a carrier opening defined by sidewalls, and conductive material is suspended by the sidewalls of the carrier opening so as to be embedded within the carrier opening, and form the conductive line.

Abstract: A conductive line is applied to a substrate by aligning the conductive line in juxtaposition with a selected area of the substrate; bonding the conductive line to the substrate; and detaching the conductive line from a carrier in which the conductive line is suspended. The carrier has a carrier opening defined by sidewalls, and conductive material is suspended by the sidewalls of the carrier opening so as to be embedded within the carrier opening, and form the conductive line.

Abstract: A module containing an electronic package provides a housing for cooling and protecting the electronic package. A top metal shell and a bottom metal shell form a common cavity in which the package is embedded without touching the inner walls of the cavity. A flexible thermally conductive foil is fixed to each of the shells. The foil is adjustable to the surface of the package and is isolated from electrically conductive parts of the package. A cooling liquid fills the gaps between the metal shells and the foils. Flexible isolated circuit means connect the package to the outside of the housing, balancing means balance pressure and volume between the shells, and further means firmly hold together the housing.

Abstract: A multiprobe apparatus for probing a device having a plurality of contacts includes a holder for holding the device in a fixed position; a plurality of electrically conducting elongated probes, each probe being adapted for electrical communication with a respective one of the contacts by tangential linear contact along the length of the probe; and a probe support for supporting the probes and for maintaining the probes in electrical communication with the contacts.

Abstract: A semiconductor light emitting/detecting device has a first doped silicon layer, an intrinsic silicon epitaxial layer formed on the first doped silicon layer, at least one quantum dot embedded within the intrinsic silicon epitaxial layer, and a second doped silicon layer formed on the second intrinsic silicon epitaxial layer.

Abstract: A conductive line is applied to a substrate by aligning the conductive line in juxtaposition with a selected area of the substrate; bonding the conductive line to the substrate; and detaching the conductive line from a carrier in which the conductive line is suspended. The carrier has a carrier opening defined by sidewalls, and conductive material is suspended by the sidewalls of the carrier opening so as to be embedded within the carrier opening, and form the conductive line.

Abstract: A wavelength of light is monitored for end-point detection during etching. Spectral data is collected during etching which characterizes variation of light emitted by discharge produced during etching. At least one principal component of the data is calculated. Each principal component has variables, each variable has a weight, and each variable corresponds to a wavelength of the light emitted by the discharge. By examining or analyzing the weights, it is then determined which variable of the principal component varies during etching such that end-point of the etch can be detected by monitoring the wavelength corresponding to the variable.

Abstract: A card structure has an internal three dimensional array of implanted semiconductor chips. The card structure includes a power core and a plurality of chip cores. Each chip core is joined to the power core on opposite surfaces of the power core, and each chip core includes a compensator core having a two dimensional array of chip wells. Each chip well allows for a respective one of the semiconductor chips to be implanted therein. Further, a compliant dielectric material is disposed on the major surfaces of the compensator core except at the bottoms of the chip wells. The compliant dielectric material has a low dielectric constant and has a thermal coefficient of expansion compatible with those of the semiconductor chips and the compensator core, so that thermal expansion stability with the chips and the compensator core is maintained.

Abstract: Punch apparatus develops momentum of a desired magnitude. The momentum is transferred to a punch for driving the punch from a reset position to a punch position.

Abstract: Automatic alignment of an optical waveguide to a ridge waveguide laser is accomplished by transferring the ridge structure of the laser to a substrate by etching a mirror groove. The transferred ridge structure serves as a base for the deposition of waveguide layers. The thickness of the waveguide layers are controlled during the deposition such that the waveguide core is laterally and vertically aligned to the lasing active layer of the laser structure.

Abstract: Process for fabricating an interconnect for a semiconductor structure, includes using a conductive etch stop layer. The conductive etch stop layer has etch selectivity to conductive interconnect material for protecting underlying features during etching. An interconnect is formed from the conductive interconnect material, and the conductive etch stop layer is caused to react with the interconnect for forming a metal alloy which electrically connects the interconnect with a structure.

Abstract: Apparatus for pressurizing a paste for dispensing the paste includes a vessel, a follower plate and a resilient seal which is movable through the vessel with the follower plate. The resiliency of the seal provides pressure for developing a seal between the seal and the vessel, and pressurized paste provides additional pressure for developing the seal.

Abstract: Alignment of an optical fiber coupled to a surface emitting or surface receiving optical element situated on a substrate wherein the optical fiber is situated in a via hole on an alignment chip. The alignment is bonded to the substrate using at least one solder bond.

Abstract: An inverted MISFET structure with a high transition temperature superconducting channel comprises a gate substrate, an interfacial layer with one or more elements of the VIII or IB subgroup of the periodic table of elements, an insulating layer and a high transition temperature superconducting channel. An electric field, generated by a voltage applied to its gate alters the conductivity of the channel.

Abstract: Process for producing a card structure having an internal three-dimensional array of semiconductor chips includes providing a thermal conductor plane, applying a first compliant dielectric material on major surfaces of the thermal conductor plane, forming a two-dimensional array of chip wells in the dielectric material on each side of the thermal conductor plane, positioning and securing semiconductor chips in the chip wells, laminating a lead frame mounted on a carrier sheet over the first compliant dielectric material and the semiconductor chips, forming an electrical connection between each of the semiconductor chips and the lead frame, encapsulating the electrical connections with a filler, laminating an insulating layer and a wiring plane over the encapsulated connections, electrically connecting the lead frame and the wiring plane so as to form a chip core, and electrically connecting a power core to the chip core.

Abstract: An improved test system includes means for generating a contact wetting pulse and applying the contact wetting pulse to a network such that contact resistance at the interfaces between probes of the test system and terminals of the network is effectively lowered.

Abstract: A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

Abstract: A plurality of individual positions arranged on a surface area are toured. The individual positions are grouped such that each group occupies a continuous partial area in the positioning plane. The groups are ordered so that the partial areas adjoin each other, forming in their totality a geometrical coarse structure. The individual positions are continuously indexed such that their sequence follows the geometrical coarse structure. The indexing of the individual positions is altered in sections such that the time required for sequentially touring all the individual positions of a section is minimized.