Abstract: An asymmetric modem communications system achieves high speed data transfers through a telephone network that includes both digital and analog communications mediums. In general, the system includes means for concurrently communicating first and second signals, respectively, in opposite directions along the connection between the communications devices and modems for modulating the first and second signals with different modulation techniques. The communications occur in full duplex manner. In a possible implementation, a digital modem is interfaced to a digital network. The digital network is connected with a coder/decoder (codec). The codec is interfaced with a two-wire analog telephone connection, sometimes referred to as a copper loop. The telephone connection is interfaced with an analog modem. Both the digital and analog modems have a transmitter and a receiver.

Abstract: A semiconductor memory device having a parallel data test scheme is disclosed. The semiconductor memory includes an array that is partitioned into array portions with each array portion further divided into sub-arrays and banks. Each array portion providing data bits to a data compression circuit. The data compression circuit includes data compare sections and ripple sections. The data compare sections include data compare circuits that compare the data bits provided by each array portion and each provide a compare output to the ripple sections. The ripple sections are coupled together in series and provide global data compare outputs. A multiplexer selects between a data bit and the global data compare outputs to provide either a data output or a data comparison output to the output pin.

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the Semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: The invention is a method of forming the art work for chemically etching that produces uniform through-etch and lateral-etch. The artwork that defines the pattern to be etched utilizes lines equal to the narrowest feature that is to be etched. Rather than etch away large areas, section are removed by etching by cutting them out of the material that is being etched. The artwork or pattern is designed with the same compensation factors throughout the entire pattern and the etch rate will be completely uniform for the entire pattern.

Abstract: A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.

Abstract: A method of discriminating noise and voice energy in a communication signal. A signal is measured in a plurality of block periods, which are sampled to obtain a measurement of the block energy value for the signal. The blocks are compared to a noise threshold and to a voice threshold to discriminate between noise and voice. The thresholds for noise and voice are periodically updated based on the minimum and maximum energy levels measured for block energies. In a preferred embodiment, the voice energy threshold and noise energy threshold values are updated according to a formula where the revised thresholds are based upon a factor of the minimum and maximum energy levels of the current block and the most recent past block and the average energy of the previous blocks. Updating of threshold levels allows for more accurate estimation of noise and voice during changes in either noise, voice or both to avoid missclassification of noise and/or voice.

Abstract: A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.

Abstract: An asymmetric modem communications system achieves high speed data transfers through a telephone network that includes both digital and analog communications mediums. In general, the system includes means for concurrently communicating first and second signals, respectively, in opposite directions along the connection between the communications devices and modems for modulating the first and second signals with different modulation techniques. The communications occur in full duplex manner. In a possible implementation, a digital modem is interfaced to a digital network. The digital network is connected with a coder/decoder (codec). The codec is interfaced with a two-wire analog telephone connection, sometimes referred to as a copper loop. The telephone connection is interfaced with an analog modem. Both the digital and analog modems have a transmitter and a receiver.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: In integrated semiconductor manufacturing, semiconductor dies may be packaged in ceramic packages. Such packages typically have a base into which the semiconductor die is placed and typically have a lid which seals the package. A halagen lamp radiant chamber significantly reduces the time it takes to seal the package.

Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N+ control gate (26) is formed in P-well (14) and includes punch-through implant region (26). NMOS transistor (16) and N+ control gate (26) have in common electrically isolated polysilicon gate (22, 32) for operating as a floating gate in common with NMOS transistor (16) and N+ control gate (26). N+ control gate (26) includes P-channel punch-through implant (34) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (10).

Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.

Abstract: In integrated semiconductor manufacturing, semiconductor dies may be packaged in ceramic packages. Such packages typically have a base into which the semiconductor die is securedly placed and typically have a lead frame securedly attached to base so that electrical connection may be made to the semiconductor die. A halagen lamp radiant chamber significantly reduces the time it takes to attach the die and lead frame to the ceramic base while reducing particles commonly associated with open belt converyor furnaces.

Abstract: A CHE programmed memory device (30) avoids forward biasing at an isolated P-well (38) junction with a deep N-well (36) and prevents emitting electrons that may cause voltage buildup across the isolated P-well region (38) by applying a forward bias current (50) or voltage source (40) connected to the deep N-well region (36) for slightly forward biasing the deep N-well region. This maintains the voltage drop of isolated P-well region (38) below the diode turn-on voltage.

Abstract: Serial data processor (16) includes a digital processor (106) , a memory controller (114) interconnected with digital processor (106), and dynamic serial access memory (112) interconnected with memory controller(134) . First data selection circuit (134) sends serial data either from serial-data-in terminal (94), from dynamic serial access memory (112), or from digital processor (106) to second serial-data-in terminal (138), in response to a first control signal. Second data selection circuit (144) sends serial data either from serial-data-in terminal (138), from dynamic serial access memory (132) or from the digital processor to serial-data-out terminal (96), in response to a second control signal. A third data selection circuit (120) sends serial data either from serial-data-in terminal (94) , from dynamic serial access memory (112), or from the digital processor (90) to third serial-data-in terminal (150), in response to a third control signal.

Abstract: Hydrofluoric acid (HF) mixed with water and often buffered with ammonium fluoride is a standard silicon dioxide wet etchant which is followed by a rinse. An improved silicon dioxide etch is vapor HF which may be followed by a water vapor rinse. The invention discloses a further improved silicon dioxide etch. Following an initial exposure to vapor HF for oxide removal, a first insitu water rinse occurs. A second exposure to vapor HF then occurs and is followed by a second insitu water rinse. Water, rather than water vapor, aids in freeing particles from the wafer surface. During both the water rinses, the wafer may be rotated at increasing speeds to aid in sweeping particles from wafer surface. The process may be practiced in a commercially available reactor and is suitable for ULSI devices having complex topographies, such as, for example, 64 megabit DRAMs employing crown type memory cells.

Abstract: A random access memory (RAM) having a bipolar reduction in array operating voltage is disclosed. In a preferred embodiment, a clamping transfer gate circuit (414) couple pairs of bit lines (BL and /BL) to pairs of sense nodes (410 and 412). The clamping transfer gate circuit (414) includes an n-channel MOS transistor (N401 and N402) in series with a p-channel MOS transistor (P401 and P402) coupling a bit line (BL or /BL) to a sense node (410 or 412). The gates of the n-channel transistors (N401 and N402) are driven by the high power supply voltage (VDD), and the gates of the p-channel transistors (P401 and P402) are driven by the low power supply voltage (VSS). A sense amplifier circuit (418) drives the sense node pair (410 and 412) to opposite power supply voltages (VDD and VSS). The n-channel transistors (N401 and N402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a maximum level of VDD-Vtn, where Vtn is the n-channel transistor threshold voltage.

Abstract: A static random access memory array (200) with power supplies and an array biasing scheme is disclosed. A power supply (202) has an output voltage that is applied to the bitlines (40). The output voltage pre-charges the bitlines (40) to read from the memory cells (10). An array power supply (204) has an array voltage that is applied to the memory cells. The array voltage is higher than the output voltage. The array power supply (204) is drived by boosting the output voltage of the power supply (202).