Abstract: In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.

Abstract: A computing device 10 is disclosed herein. A base unit 12 is provided for housing a plurality of computing components and also may include an input/output device such as a keyboard. A display unit 20 can be pivotally coupled to the base unit 12 about a spine 26a. The display unit 20 may include a viewing surface 24. In addition, a flap 50 can be attached to at least one edge of the display 20 and extend outwardly from screen 24. Electronic components 46 may be housed within the flap 50. Alternatively, the electronic components 46 may be housed within the base unit 12 and electrically coupled back to the display units 20.

Abstract: In a surface mount assembly, an active integrated circuit device, such as, for example, a dynamic random access memory, typically has a lead finger attached to a solder pad of a printed wiring board. The surface mount assembly is significantly improved by configuring a passive component, such as a resistor or capacitor, such that it has metallic terminations on an upper and lower surface so that it may be positioned between the solder pad of the printed wiring board and the lead finger.

Abstract: A phase/frequency detector (18) includes a first memory circuit (50), a second memory circuit (52), a first set circuit (54), a second set circuit (58) and a reset circuit (56). The first memory circuit (50) provides a first output signal (20) in response to the first input signal (12). The second memory circuit (52) provides a second output signal (22) in response to the second input signal (14). The first set circuit (54) initiates the transition of the first memory circuit (50) to the active state, and the second set circuit (58) initiates the transition of the second memory circuit (52) to the active state. The reset circuit (56) initiates the transition of the memory circuits (50, 52) to the inactive state.

Abstract: A circuit for reducing the stand-by current of semiconductor device is disclosed in a number of embodiments. In a first embodiment, a first conductive line (302), such as a bit line or common capacitor plate in a DRAM, is charged to a first potential in a stand-by state. A second conductive line (304), such as a word line in a DRAM, is driven to the first potential in the stand-by state in the event a short circuit condition exists between the first conductive line (302) and the second conductive line (304). In a second embodiment, a second conductive line (404) in a semiconductor device is 34w isolated from other circuits in the semiconductor device in a stand-by mode. This allows the second conductive line (404) to rise to a short circuit potential in the event a short circuit condition exists between the second conductive line (404) and a short circuit potential.

Abstract: An apparatus and method for forming thin film aerogels on semiconductor substrates is disclosed. It has been found that in order to produce defect.about.free nanoporous dielectrics with a controllable high porosity, it is preferable to substantially limit evaporation and condensation of pore fluid in the wet gel thin film, e.g. during gelation, during aging, and at other points prior to obtaining a dried gel. The present invention simplifies the atmospheric control needed to prevent evaporation and condensation by restricting the atmosphere in contact with the wet gel thin film to an extremely small volume. In one embodiment, a substrate 26 is held between a substrate holder 36 and a parallel plate 22, such that a substantially sealed chamber 32 exists between substrate surface 28 and chamber surface 30. Preferably, the average clearance between surfaces 28 and 30 is less than 5 mm, or more preferably, less than 1 mm.

Abstract: A read mask circuit (300) is disclosed. A mask command is shifted through a series of mask latches (308 and 310) to generate the output-enable input (OE.sub.--) of an output driver (306). In synchronism with the mask command, data bits are shifted through a series of data latches (312 and 314) to the data input (DIN) of the output driver (306). To prevent a race condition between the mask command and the data bit that is to be masked (B3), the mask command, when latched in the second-to-last mask latch (308), is used to interrupt the last data latch (314). This prevents the to-be-masked data bit (B3) from being latched in the last data latch (314) and generating an undesirable output data transition by the output driver (306).

Abstract: The present invention includes a circuit for detecting voltage levels in an integrated circuit including a first reference voltage(324), a first differential amplifier(349) having an inverting input terminal connected to the first reference voltage, a non-inverting input terminal and an output terminal, a first transistor (356) having a control terminal connected to the output terminal of the first differential amplifier, having a first current handling terminal connected to a voltage supply terminal and having a second current handling terminal connected to the non-inverting input terminal of the first differential amplifier, a first load (358) device having a first terminal connected to the second current handling terminal of the first transistor and a second terminal, a second load device (360) having a first terminal connected to the second of the first load device and a second terminal connected to a second reference potential, a second differential amplifier (391) having an inverting input terminal, a n

Abstract: An integrated circuit (SAI.sub.0) comprises a first SOI transistor (T4) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. The integrated circuit further includes a second SOI transistor (T5) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. In the integrated circuit, one of the plurality of nodes of the first SOI transistor is connected to receive a first differential input signal.

Abstract: A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240).

Abstract: A method is provided for accurate patterning of photoresist during lithography process. A photoresist layer is deposited on a surface of a semicondictor wafer. The photoresist layer is then illuminated using a lithography apparatus including a mask, a two-thirds annular aperture stop and a quadra pole aperture stop. Portions of the photoresist layer are removed to provide a resulting patterned photoresist layer.

Abstract: A ferroelectric random access memory (FeRAM) is disclosed. The FeRAM (400) provides a folded bit line array having memory cells (402a-402f and 404a-404d) with an area equivalent to 6F.sup.2, where F is a minimum feature size. Reduced array size is achieved by utilizing access transistors of complementary conductivity type within the array. First type memory cells (402a-402f) having n-channel access transistors (N400a-N400f), are formed next to second type memory cells (404a-404d) having p-channel access transistors (P400a-P400d). Bit lines (410a-410e) are arranged into bit line pairs, with a first bit line of each pair being coupled to first type memory cells (402a-402f) and the second bit line of each bit line pair being coupled to second type memory cells (404a-404d). When a word line is driven to a first voltage, ferroelectric capacitor data is driven on the first bit line, while the second bit line provides a reference voltage.

Abstract: According to one aspect of the present invention, a selectable integrated circuit assembly (10) is disclosed. The assembly includes a first plurality of terminals (20) for communicating information to and from an integrated circuit device and a second plurality of terminals (22) for receiving an assembly address. The assembly (10) also includes select logic (14) connected to receive the assembly address and operable to generate select signals based upon the assembly address. The select signals have a selected state and a not-selected state. A plurality of switches (18) are connected between the first plurality of terminals (20) and the integrated circuit device. The plurality of switches (18) are connected to receive the select signals. The switches (18) operate, when the select signals are in the selected state, to connect the first plurality of terminals (20) to the integrated circuit device.

Abstract: A random access memory (RAM) (700) is disclosed which includes a reduced page size for decreasing power consumption, and a unique input/output (I/O) arrangement for maintaining a relatively large I/O space, without substantially increasing the number of I/O lines within the RAM. The RAM (700) includes a number banks (704) each of which is logically divided into even array sections and odd array sections (900). Data from the array sections (900) is coupled to I/O select blocks (914, 916, 918, 920) by groups of local I/O lines (902, 904, 906, 908). According to an applied address, the sense amplifiers within the even array sections are activated, indicating an "even" sense cycle, or the sense amplifiers within the odd array sections are activated, indicating an "odd" sense cycle. In an even sense cycle, the I/O select blocks (914, 916, 918, 920) couple the LIO line groups of the even array sections (900) to global I/O lines (910, 912).

Abstract: An integrated biochemical sensor (200) for detecting the presence of one or more specific samples (240) having a device platform (355) with a light absorbing upper surface and input/output pins (375) is disclosed. An encapsulating housing (357) provides an optical transmissive enclosure which covers the platform (355) and has a layer of fluorescence chemistry on its outer surface (360). The fluorophore is chosen for its molecular properties in the presence of the sample analyte (240). The detector (370), light sources (365, 367, 407, 409) are all coupled to the platform (355) and encapsulated within the housing (357). A filter (375) element is used to block out unwanted light and increase the detector's (370) ability to resolve wanted emission light.

Abstract: An integrated circuit device having a memory array (50) with segmented bit lines and a method of operation are disclosed. A sub array (52) of the memory array (50) can be operated as a multiple port sub array. A bit line of the sub array (52) is separated into bit line segments by disconnecting the bit line segments (54) from one another. A first bank of sense amplifiers (58) is connected to a first bit line segment (54) of the sub array (52), and a second bank of sense amplifiers (58) is connected to a second bit line segment (54) of the sub array (52). A first operation is performed to the first bit line segment (54) using the first bank of sense amplifiers (58), and a second operation is concurrently performed to the second bit line segment (54) using the second bank of sense amplifiers (58).

Abstract: The described embodiments of the present invention provide a computer docking station (12, 32, 58, 68, 76, 84, 90, 92, 94, 96) that can have its functionality reconfigured by a docked portable personal computer (10, 38, 62, 66, 74, 82). In at least one embodiment of the invention, the computer docking station is configured as a stand alone computer prior to docking with a portable computer, may have its functionality reconfigured when docked to the portable computer, and reconfigures itself to be a stand alone computer when undocked from the portable computer. In one embodiment of the invention, docking station resources are placed under the control of a docked portable computer. In another embodiment of the invention, docked portable computer resources are placed under the control of the docking station.

Abstract: A two stage input buffer substantially reduces propagation delay by triggering only off of the rising edge of the external clock signal, eliminating a pulse generator, and setting the pulse width via feedback through a fixed delay. An unbalanced driver reduces capacitance on the N-channel transistor. In a memory application, such as in a synchronous dynamic random access memory, access time is improved, margin is advantageously added to the hold time requirement, and driver fan out capabilities are improved.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) silicon-oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium silicon-oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium silicon-oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide. However, the zirconium silicon-oxynitride gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability.

Abstract: A method of preparing a surface for and forming a thin film on a single-crystal silicon substrate is disclosed. One embodiment of his method comprises forming an oxidized silicon layer (which may be a native oxide) on at least one region of the substrate, and thermally annealing the substrate in a vacuum while supplying a silicon-containing flux to the oxide surface, thus removing the oxidized silicon layer. Preferably, the thin film is formed immediately after removal of the oxidized silicon layer. The silicon-containing flux is preferably insufficient to deposit a silicon-containing layer on top of the oxidized silicon layer, and yet sufficient to substantially inhibit an SiO-forming reaction between the silicon substrate and the oxidized silicon layer. The method of the invention allows for growth or deposition of films which have exceptionally smooth interfaces (less than 0.1 nm rms roughness) with the underlying silicon substrate at temperatures less than 800.degree. C.