Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches connected in series, the first switch being connected to an upper power supply and the third switch being connected to a lower power supply. The output of the circuit is connected to a circuit node located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit which provides a further output to control the first switch. The second switch is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage.

Abstract: A circuit for generating an output voltage which is proportional to temperature with a required gradient is disclosed. The circuit relies on the principle that the difference in the base emitter voltage of two bipolar transistors with differing areas, if appropriately connected, can result in a current which has a positive temperature coefficient, that is a current which varies linearly with temperature such that as the temperature increases the current increases. It is important to maintain a stable internal line voltage in the face of significant variations in a supply voltage to the circuit. This is achieved herein by providing control elements appropriately connected to a differential amplifier. The stable internal supply voltage can be used to power a subsequent stage of the circuit for fine control of the gradient of the voltage proportional to temperature.

Abstract: A circuit for providing a control signal for a load includes a first switch having a first and a second state, a second switch having a first and a second state coupled to said first switch, a load connected to said first and second switches, protection circuitry for protecting said load from excessive voltage and circuitry for switching said first switch. The circuit is arranged so that when the first switch is in the first state current flows from the load to the first switch and the switching circuitry is arranged to switch the first switch to the second state when the voltage across the load reaches a predetermined value.

Abstract: A circuit for generating an output voltage proportional to temperature with a required gradient, the circuit including a first stage arranged to generate a first voltage which is proportional to temperature with a predetermined gradient but has a positive value when the temperature falls below zero and a second stage connected to the first stage and including a differential amplifier having a first input connected to receive the first voltage and a second input connected to receive a feedback voltage which is derived from an output signal of the differential amplifier via an offset circuit which introduces an offset voltage such that the output signal of the differential amplifier provides at an output node the output voltage which has a negative variation with negative temperatures.

Abstract: An ATM routing switch has a buffer circuit for holding cells located on queues at output ports, the buffer having a first reserve buffer capacity for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.

Abstract: High density MOS technology power device structure, including body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein the body regions include at least one plurality of substantially rectilinear and substantially parallel body stripes each joined at its ends to adjacent body stripes by junction regions, so that the at least one plurality of body stripes and the junction regions form a continuous, serpentine-shaped body region.

Abstract: Apparatus for re-assembling information cells of messages, comprising a message memory, a message data memory, a location memory, and loading apparatus. The message memory stores each message in blocks that can be different lengths. The message data memory stores, for each message, message data defining a location in message memory, a position in the block, and a length of the block that is to receive the cells of the message. The location memory stores, for each message, an indication of the location of the message data. The loading apparatus receives the cells, and for each cell, accesses location memory to determine the location of message data, stores the cell in the message memory at the indicated location, increments the message data defining the location and the position, and compares the incremented position with the stored length of the block to determine whether the end of the block has been reached.

Abstract: The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.

Abstract: An integrated current reference comprises two current mirrors, the gate source voltage of one of the current mirrors being offset by a voltage reference element, which in an embodiment consists of an on MOSFET.

Abstract: A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.

Abstract: The transmission of interrupts is described where the interrupt is represented at a peripheral device by the electrical level of a conductor but where it is conveyed to a receiving module by way of a message packet routed along a routing path. According to one aspect, the message packet includes the identification of the peripheral device which generated the interrupt and the receiving module acts on the message packet to implement an interrupt handling routine depending on the identification of the peripheral device. According to another aspect, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts, and the receiving module generates a response packet containing that transaction identifier thereby allowing the peripheral device to monitor whether or not its interrupts have been treated properly.

Abstract: A single integrated circuit chip connected to an external computer device. The chip includes a CPU with registers, a bus for addressing devices assigned to a memory address space of the CPU and providing a parallel path between the CPU and a first memory local to the CPU, an address memory for storing addresses assigned to the devices, and an external port connected to the bus. The port includes an internal parallel signal format connection to the bus and a less parallel external connection to the external computer device. The port forms part of the memory address space of the CPU. The external computer device includes a second memory local to the external computer device and accessible by the CPU through the port. Address diversion means are provided for reconfiguring the memory address space of the CPU to assign to the port memory addresses of another one of the devices.

Abstract: A voltage converter comprises an input, an output and a current control arrangement for controlling the output current of the voltage converter circuit. The current control arrangement comprises a first mode, when the voltage output by the converter circuit is above a threshold voltage, and a second mode in which the voltage output by the circuit is below the threshold voltage. The first and second modes are controlled by the same current control arrangement. The current control arrangement comprises comparing means arranged to receive a reference voltage wherein the reference voltage is a voltage offset associated with at least one of the inputs of the comparing means.

Abstract: A cache system and method of operating are described in which a cache is connected between a processor and a main memory of a computer. The cache system includes a cache memory having a set of cache partitions. Each cache partition has a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor. The cache system also includes a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations in a cache partion wich depends on the address of said item in the main memory. This is achieved by a cache partition access table holding in association with addresses of items to be cached respective multi-bit partition indications identifying one or more cache partition into which the item is to be loaded.

Abstract: A circuit for controlling the storage of data in a memory element including a bistable device having a first input for receiving an address input and a second input for receiving a clock signal and circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for the memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, the first and next transitions being in the same clock cycle.

Abstract: A computer is operated to generate electronic data defining a system model by loading into the computer a class definition defining instructions which are processed by the system, the definition including a set of functional methods to which the instruction is subjected by the system and a set of locations for members representing the instruction. A model execution program is then executed on the computer which calls the class definition for each instruction, invokes one of the functional methods and loads the locations of the entry with state information depending on the functional method to create a functional component. The functional component is loaded into memory and the state information of the functional component modified independence on a subsequently invoked functional method by the model execution program.

Abstract: A circuit for generating an output voltage proportional to temperature with a required gradient, the circuit including a first stage arranged to generate a first voltage which is proportional to temperature with a predetermined gradient, the first stage including first and second bipolar transistors with different emitter areas having their emitters connected together and their bases connected across a bridge resistive element, wherein the collectors of the transistors are connected to an internal supply line via respective matched resistive elements as the voltage across the bridge resistive element is proportional to temperature; a differential amplifier having its input connected respectively to the collectors, and its output connected to stabilisation circuitry connected between first and second power supply rails and an internal supply line which cooperates with the differential amplifier to maintain a stable voltage on the internal supply line despite variations between the first and second power supply

Abstract: A single chip integrated circuit device includes a breakpoint range unit having first and second breakpoint registers for holding respectively lower and upper breakpoint addresses between which normal operation of the CPU is to be interrupted for diagnostic purposes. The breakpoint range unit further has comparison logic operative to compare the contents of the address register with each of a lower and upper breakpoint address, and to issue a breakpoint signal when the address held in an address register is equal to the lower breakpoint address or between the lower and upper breakup addresses. On chip control logic is connected to receive the breakpoint signal and arranged to interrupt normal operation of the CPU when the breakpoint signal is received. The comparison logic includes inverse state logic configured to set an inverse state indicator to cause generation of the breakpoint signal outside the address range defined by the upper and lower breakpoint address.

Abstract: The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern and the storage of this test pattern in a first test register, this providing step being synchronized by an external clock signal; serially providing of this test pattern to an input of the internal logic circuit, this providing step being synchronized by a test clock signal generated from an internal clock signal; storing, in a second test register connected to the output of the internal logic circuit, at least one resulting pattern generated by the internal logic circuit when the test pattern is provided thereto, this storing being synchronized by the test clock signal; and providing to the outside, by series shifting, of the resulting pattern, this providing step being synchronized by the external clock signal.

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed