Abstract: A ratio logic gate has a current mirror controlled by the pull-down transistors and supplying a half size pull-down transistor. When one or more of the input pull-down transistors is on, the mirror current overcomes the output pull-down transistor to provide a high potential output. Process tolerances between p and n type devices is thus avoided.

Abstract: A complementary logic circuit is provided which provides improved switching times over known complementary logic circuits. The circuit includes a further n-type transistor connected in series between a p-type and an n-type transistor. This additional n-type transistor has its gate permanently connected to an upper supply voltage, Vdd. When switching occurs the n-type transistor is effectively open circuit. This allows the first n-type transistor to switch on by a substantial amount quite quickly without ‘fighting’ the presently conducting p-type transistor. When the first n-type transistor has been turned substantially on second transistor becomes conductive. Then the p-type transistor is substantially turned off and no longer opposes the turning on of the first n-type transistor.

Abstract: There is disclosed a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device. The chip has a CPU and a communication bus providing a parallel communication path between the CPU and the first local memory. The chip further comprises an external communication port connected to the bus, the external computer device being connected to an external communication port and having a second memory. The port has an internal connection of an internal parallel signal format and an external parallel signal format and an external connection of an external format less parallel than the internal format. The second memory is accessible by the CPU through the port, the port forming part of the memory address space of the CPU from which instructions may be fetched. The port may be addressed by execution of an instruction by said CPU. There is also discloses a method of operating such a computer system.

Abstract: The present invention relates to a control circuit of a vibrating membrane excited by a solenoid in series with a d.c. supply and a controlled switch. A capacitor is disposed across a series circuit including the solenoid and the switch associated with opening means in the vicinity of a zero crossing of the current in the inductance.

Abstract: A flip-flop circuit comprises a pair of cross-coupled inverters, each of which has a respective FET connected in series between it and the reference terminal, each inverter driving a transistor of an output inverter.

Abstract: A wordline driver has enable circuitry optimized for positive-going input transitions and disable circuitry optimized for transitions in a disable input which would cause the output to become disabled. The optimization is achieved by suitably dimensioning the transistors in the respective enable and disable circuits for suitable current-carrying ability.

Abstract: A miss detector for a content addressable memory has plural input lines connected across points with the memory output lines. The detector input lines are disposed in pairs of true and false lines, and gating circuitry gates together the true and false pairs to provide a miss error message.

Abstract: An output circuit which can minimize the delay in combining two clocks comprises a multiplexer with a flip flop connected to one input and a clocked latch connected to the other. The clocked latch is transparent during one clocking state so that changes to its input appear directly at its output.

Abstract: An integrated current reference circuit uses two current mirror circuits, in which one of the transistors of one of the current mirrors has a back gate connection to the power rail, the drain-source path being connected to the power rail via a voltage offset element.