Abstract: A method, computer program product and data processing system for identifying and modifying the format of keys in a resource file source code and in the associated a program code. In one embodiment of the present invention, a program reads a resource file source code for keys written in a non-standard format. Upon detecting one or more keys written in a non-standard format in the resource file source code, the program modifies the format of those one or more keys so that they are written in a standard format. The program may then read the associated program code for any text that matches the written format of the one or more keys written in the non-standard format. Upon detecting any text that matches the written format of the one or more keys written in the non-standard format, the program replaces any matched text with the updated written format, i.e. standard format, of the one or more keys whose format was modified.

Abstract: A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.

Abstract: A method, computer program product and system for detecting a first-hop dead gateway. In one embodiment, a method comprises the step of sending a TCP packet of data from an application of a sender host to a receiver host through a first gateway, where the first gateway is a first-hop away from the sender host. The method further comprises the step of TCP failing to receive an acknowledgment of received data from the receiver host. The method further comprises the step of deleting an ARP entry associated with the first gateway in the sender host. The method further comprises the step of establishing a new communication using the first gateway by the application or new application of the sender host. The method further comprises the step of sending an ARP request to the first gateway by the sender host.

Abstract: A timer management system and method for managing timers in both a synchronous and asynchronous system. In one embodiment of the present invention, a timer management system comprises an application program interface (API) for providing a set of synchronous functions allowing an application to functionally operate on the timer. The timer management system further comprises a timer database for storing timer-related information. Furthermore, the timer management system comprises a timer services for detecting the expiring of the timer. A handle function of the timer services allows an asynchronous application, i.e., application in a multi-task system, to synchronously act on the timer. That is, when a timer in a asynchronous system times-out, the handle function allows the asynchronous application to act on the expired timer without incurring an illegal time-out message.

Abstract: A method, network system and computer program product for establishing a server node in a virtual private network with a single tunnel definition and a single security policy for a plurality of tunnels associated with a group name. In one embodiment, a method comprises the step of configuring a group database in the server node. The group database in the server node comprises the group name and a list of members associated with the group name. The method further comprises configuring a rules database in the server node. The rules database associates the group name with a particular security policy. The method further comprises configuring a tunnel definition database in the server node. In the tunnel definition database, the remote ID is defined as the group name. In another embodiment of the present invention, the list of members associated with the group name comprises a non-contiguous list of ID types.

Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: A method and circuit for mitigating gate leakage during a sleep state. An input pattern may be applied to one or more of a plurality of devices in a circuit, e.g., static circuit, dynamic circuit, during a sleep state. In response to the application of the input pattern, a majority of the devices in the circuit may have a substantially identical voltage at each of its terminals, i.e., the source, gate and drain terminal, thereby mitigating gate leakage.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A method, computer program product and system for monitoring and locating an object using secure communications without relying on GPS. A monitoring device may activate a monitored unit (unit monitored by monitoring device) by transmitting a seed of an algorithm and a time synchronization to the monitored unit. The seed and time synchronization may be used in conjunction with an algorithm, e.g., frequency hopping table, stored in both the monitoring device and the monitored unit, to allow both the monitoring device and the monitored unit to communicate with one another at a uniquely synchronized time and frequency thereby making it more difficult for a third party to locate the monitored unit. An alert may be generated when the monitored unit is located beyond a predetermined zone. The monitored unit may be located by activating a directional antenna in conjunction with a digital compass on the monitoring device.

Abstract: A system for minimizing the length of the longest diagonal interconnection. A multiple chip module may comprise a first chip connected to a second chip located diagonally to the first chip. The first and second chip are interconnected by one or more interconnections commonly referred to as diagonal interconnections. Since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the longest orthogonal interconnection. Furthermore, since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the second longest diagonal interconnection.

Abstract: A method, system and computer program product for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (“interconnections of interest”). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist.

Abstract: A method, computer program product and system for estimating the number of internationalization faults, e.g., errors, warnings, in a software program. The number of internationalization faults may be estimated by scanning a subset of the total lines of code in a software program. A first factor may be calculated based on a count and the number of faults identified in the lines of code scanned. A second factor may be calculated based on the number of faults remaining after subtracting the number of faults identified in error from the number of faults identified in the lines of code scanned as well as the number of faults identified in the lines of code scanned. An estimate of the number of faults in the entire software program may be calculated based on the first and second factor and the count of the total number of lines of code in the software program.

Abstract: A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

Abstract: A system, method and article of manufacturing for increasing link bandwidth occupation in a high speed packet switching digital network by enabling merging the traffics provided by different source users over several network node entry ports and to be propagated throughout network paths toward a same destination network port. To that end, at network ingress, the original packets provided by said source users and entering the network, are encapsulated with a so-called Single Sided Virtual Channel (SSVC) header including a Data Link Connection Identification (DLCI) field. Then, the packets provided by said source users and entering a given network node along their predefined path are monitored. Said packets SSVC headers DLCI fields are loaded with a same Virtual Channel number, whereby the corresponding traffics are being merged into a same channel, down to the destination network node. Then, the packets in said destination node are de-encapsulated from said SSVC header.

Abstract: A method, computer program product and data processing system for accessing extended attributes. An extended attribute descriptor in a dinode may be read to determine if there exists extended attributes associated with a file system object that is associated with the dinode. An extended attribute descriptor points to a dinodex associated with the dinode if there exists an extended attribute associated with the file system object. The dinodex may then be read to retrieve the extended attritbutes stored either inside or outside the dinodex. However, if there is no extended attribute associated with that particular file system object, then the extended attribute descriptor comprises a null value and does not point to a dinodex associated with the dinode.

Abstract: A method and system for projecting an image. An image projection system may include a sensor configured to detect the presence of an observer within a proximity of a medium, e.g., screen, window. In response to the sensor detecting the presence of an observer within a proximity of the medium, one or more portions of the medium may be switched from a transparent state to a substantially translucent state. At a substantially concurrent time as switching the one or more portions of the medium to a substantially translucent state, an image may be projected onto such portion(s). Hence, an image may be displayed in response to detecting an observer within the proximity of the medium.

Abstract: A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.

Abstract: In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back.

Abstract: The present invention provides a method and system for polishing a wafer surface. The method and system comprises determining whether a thickness of the wafer surface is uniform while the wafer surface is being polished, and adjusting the polishing process while the wafer surface is being polished based on the determination of whether the thickness of the wafer surface is uniform. Through the use of the method and system in accordance with the present invention, in-situ adjustments can be made to the CMP polishing process while the wafer is actually being polished. This results in a substantial improvement in polishing uniformity.