Abstract: A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps.

Abstract: An apparatus and method for detecting speed variations across a die, a flash field, i.e., multiple dies, and multiple flash fields. In one embodiment, a method comprises the step of inserting a plurality of functional circuits at strategic locations across a die or flash field or multiple flash fields where each of the plurality of functional circuits generates data, e.g., values, frequency, etc., correlated to the die speeds at the strategic locations. The method further comprises reading the data generated by the plurality of functional circuits that may be correlated to the die speeds at the strategic locations. Speed variations across the die or flash field or multiple flash fields may then be subsequently detected based on the data generated by the plurality of functional circuits. Upon analyzing the data generated by the plurality of functional circuits, adjustments may be made to the manufacturing process to improve the number of acceptable integrated circuits or chips disposed in the dies.

Abstract: A method for electrically quantifying a semiconductor device's spacers' width. In one embodiment, a method comprises the step of measuring a resistance across a region of interest of each of a plurality of semiconductor structures including the semiconductor device in question, where the region of interest may be a source or drain region of the semiconductor structure or may be one of a plurality of lightly doped drain regions of the semiconductor structure. The method further comprises determining a width of one of a plurality of lightly doped drain regions of the semiconductor device from the resistance across the region of interest of each of the plurality of semiconductor structures. The method further comprises determining the semiconductor device's spacers' width from the width of one of the plurality of lightly doped drain regions of the semiconductor device.